1*77b55e8cSThomas Abraham /* 2*77b55e8cSThomas Abraham * (C) Copyright 2010 Samsung Electronics 3*77b55e8cSThomas Abraham * Naveen Krishna Ch <ch.naveen@samsung.com> 4*77b55e8cSThomas Abraham * 5*77b55e8cSThomas Abraham * SPDX-License-Identifier: GPL-2.0+ 6*77b55e8cSThomas Abraham * 7*77b55e8cSThomas Abraham * Note: This file contains the register description for SROMC 8*77b55e8cSThomas Abraham */ 9*77b55e8cSThomas Abraham 10*77b55e8cSThomas Abraham #ifndef __ASM_ARCH_SROMC_H_ 11*77b55e8cSThomas Abraham #define __ASM_ARCH_SROMC_H_ 12*77b55e8cSThomas Abraham 13*77b55e8cSThomas Abraham #define SROMC_DATA16_WIDTH(x) (1<<((x*4)+0)) 14*77b55e8cSThomas Abraham #define SROMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/ 15*77b55e8cSThomas Abraham /* 1-> Byte base address*/ 16*77b55e8cSThomas Abraham #define SROMC_WAIT_ENABLE(x) (1<<((x*4)+2)) 17*77b55e8cSThomas Abraham #define SROMC_BYTE_ENABLE(x) (1<<((x*4)+3)) 18*77b55e8cSThomas Abraham 19*77b55e8cSThomas Abraham #define SROMC_BC_TACS(x) (x << 28) /* address set-up */ 20*77b55e8cSThomas Abraham #define SROMC_BC_TCOS(x) (x << 24) /* chip selection set-up */ 21*77b55e8cSThomas Abraham #define SROMC_BC_TACC(x) (x << 16) /* access cycle */ 22*77b55e8cSThomas Abraham #define SROMC_BC_TCOH(x) (x << 12) /* chip selection hold */ 23*77b55e8cSThomas Abraham #define SROMC_BC_TAH(x) (x << 8) /* address holding time */ 24*77b55e8cSThomas Abraham #define SROMC_BC_TACP(x) (x << 4) /* page mode access cycle */ 25*77b55e8cSThomas Abraham #define SROMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */ 26*77b55e8cSThomas Abraham 27*77b55e8cSThomas Abraham #ifndef __ASSEMBLY__ 28*77b55e8cSThomas Abraham struct s5p_sromc { 29*77b55e8cSThomas Abraham unsigned int bw; 30*77b55e8cSThomas Abraham unsigned int bc[4]; 31*77b55e8cSThomas Abraham }; 32*77b55e8cSThomas Abraham #endif /* __ASSEMBLY__ */ 33*77b55e8cSThomas Abraham 34*77b55e8cSThomas Abraham /* Configure the Band Width and Bank Control Regs for required SROMC Bank */ 35*77b55e8cSThomas Abraham void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf); 36*77b55e8cSThomas Abraham 37*77b55e8cSThomas Abraham enum { 38*77b55e8cSThomas Abraham FDT_SROM_PMC, 39*77b55e8cSThomas Abraham FDT_SROM_TACP, 40*77b55e8cSThomas Abraham FDT_SROM_TAH, 41*77b55e8cSThomas Abraham FDT_SROM_TCOH, 42*77b55e8cSThomas Abraham FDT_SROM_TACC, 43*77b55e8cSThomas Abraham FDT_SROM_TCOS, 44*77b55e8cSThomas Abraham FDT_SROM_TACS, 45*77b55e8cSThomas Abraham 46*77b55e8cSThomas Abraham FDT_SROM_TIMING_COUNT, 47*77b55e8cSThomas Abraham }; 48*77b55e8cSThomas Abraham 49*77b55e8cSThomas Abraham struct fdt_sromc { 50*77b55e8cSThomas Abraham u8 bank; /* srom bank number */ 51*77b55e8cSThomas Abraham u8 width; /* bus width in bytes */ 52*77b55e8cSThomas Abraham unsigned int timing[FDT_SROM_TIMING_COUNT]; /* timing parameters */ 53*77b55e8cSThomas Abraham }; 54*77b55e8cSThomas Abraham 55*77b55e8cSThomas Abraham #endif /* __ASM_ARCH_SROMC_H_ */ 56