Home
last modified time | relevance | path

Searched refs:MHZ (Results 1 – 20 of 20) sorted by relevance

/rk3399_rockchip-uboot/drivers/video/exynos/
H A Dexynos_mipi_dsi_common.c18 #define MHZ (1000 * 1000) macro
19 #define FIN_HZ (24 * MHZ)
21 #define DFIN_PLL_MIN_HZ (6 * MHZ)
22 #define DFIN_PLL_MAX_HZ (12 * MHZ)
24 #define DFVCO_MIN_HZ (500 * MHZ)
25 #define DFVCO_MAX_HZ (1000 * MHZ)
110 delay_val = MHZ / dsim->dsim_config->esc_clk; in exynos_mipi_dsi_wr_data()
289 if (dfin_pll < 7 * MHZ) in exynos_mipi_dsi_change_pll()
291 else if (dfin_pll < 8 * MHZ) in exynos_mipi_dsi_change_pll()
293 else if (dfin_pll < 9 * MHZ) in exynos_mipi_dsi_change_pll()
[all …]
/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_pll.c35 #define MHZ 1000000 macro
38 #define OSC_HZ (24UL * MHZ)
39 #define VCO_MAX_HZ (3200UL * MHZ)
40 #define VCO_MIN_HZ (800UL * MHZ)
41 #define OUTPUT_MAX_HZ (3200UL * MHZ)
42 #define OUTPUT_MIN_HZ (24UL * MHZ)
43 #define MIN_FOUTVCO_FREQ (800UL * MHZ)
44 #define MAX_FOUTVCO_FREQ (2000UL * MHZ)
46 #define RK3588_VCO_MIN_HZ (2250UL * MHZ)
47 #define RK3588_VCO_MAX_HZ (4500UL * MHZ)
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Drockchip_dmc.h10 #ifndef MHZ
11 #define MHZ (1000 * 1000) macro
H A Dsdram_common.h9 #ifndef MHZ
10 #define MHZ (1000 * 1000) macro
/rk3399_rockchip-uboot/board/freescale/bsc9132qds/
H A DREADME94 make BSC9132QDS_NOR_DDRCLK100 : For 100MHZ DDR CLK
95 make BSC9132QDS_NOR_DDRCLK133 : For 133MHZ DDR CLK
98 make BSC9132QDS_SPIFLASH_DDRCLK100 : For 100MHZ DDR CLK
99 make BSC9132QDS_SPIFLASH_DDRCLK133 : For 133MHZ DDR CLK
101 make BSC9132QDS_SDCARD_DDRCLK100 : For 100MHZ DDR CLK
102 make BSC9132QDS_SDCARD_DDRCLK133 : For 133MHZ DDR CLK
/rk3399_rockchip-uboot/board/freescale/b4860qds/
H A Db4_pbi.cfg25 #slowing down the MDC clock to make it <= 2.5 MHZ
/rk3399_rockchip-uboot/board/freescale/t208xqds/
H A Dt208x_pbi.cfg32 #Errata for slowing down the MDC clock to make it <= 2.5 MHZ
/rk3399_rockchip-uboot/board/freescale/t208xrdb/
H A Dt2080_pbi.cfg32 #Errata for slowing down the MDC clock to make it <= 2.5 MHZ
/rk3399_rockchip-uboot/arch/m68k/cpu/mcf5445x/
H A Dspeed.c28 #define MHZ 1000000 macro
208 if (bus <= CLOCK_PLL_FSYS_MIN - MHZ) in setup_5445x_clocks()
/rk3399_rockchip-uboot/arch/m68k/cpu/mcf5227x/
H A Dspeed.c28 #define MHZ 1000000 macro
/rk3399_rockchip-uboot/drivers/ram/rockchip/
H A Drockchip_dmc.c872 if (freq < MHZ) in set_ddr_freq()
873 freq *= MHZ; in set_ddr_freq()
H A Dsdram_rk3328.c81 u32 mhz = hz / MHZ; in rkclk_set_dpll()
129 rkclk_set_dpll(dram, sdram_params->base.ddr_freq * MHZ * 2); in rkclk_configure_ddr()
H A Dsdram_rv1126.c393 rkclk_set_dpll(dram, sdram_params->base.ddr_freq * MHZ / 2); in rkclk_configure_ddr()
1257 phy_pll_set(dram, sdram_params->base.ddr_freq * MHZ, 0); in phy_cfg()
2584 phy_pll_set(dram, sdram_params->base.ddr_freq * MHZ, 1); in sdram_init_()
H A Dsdram_rk3399.c2908 dfs_configs[ctl_fn].base.ddr_freq / MHZ, ctl_fn, phy_fn); in set_rate0()
2922 dfs_configs[ctl_fn].base.ddr_freq / MHZ, ctl_fn, phy_fn); in set_rate1()
H A Dsdram-rk3399-lpddr4-400.inc51 .ddr_freq = 400*MHZ,
H A Dsdram-rk3399-lpddr4-800.inc51 .ddr_freq = 800*MHZ,
/rk3399_rockchip-uboot/cmd/ddr_tool/ddr_dq_eye/
H A Dddr_dq_eye.c221 result.fsp_mhz[fsp] == (u16)(freq_mhz / MHZ)) in do_ddr_dq_eye()
/rk3399_rockchip-uboot/board/freescale/mpc8641hpcn/
H A DREADME65 SW6(3-5) = 000 CONFIG_SYS_REFCLKSEL = 000 :: 100MHZ
/rk3399_rockchip-uboot/board/freescale/m52277evb/
H A DREADME144 CPU CLK 160 Mhz BUS CLK 80 Mhz FLB CLK 80 MHZ
/rk3399_rockchip-uboot/
H A DREADME578 converts clock data to MHZ before passing it to the