18 #define MHZ			(1000 * 1000)  macro
19 #define FIN_HZ			(24 * MHZ)
21 #define DFIN_PLL_MIN_HZ		(6 * MHZ)
22 #define DFIN_PLL_MAX_HZ		(12 * MHZ)
24 #define DFVCO_MIN_HZ		(500 * MHZ)
25 #define DFVCO_MAX_HZ		(1000 * MHZ)
110 	delay_val = MHZ / dsim->dsim_config->esc_clk;  in exynos_mipi_dsi_wr_data()
289 		if (dfin_pll < 7 * MHZ)  in exynos_mipi_dsi_change_pll()
291 		else if (dfin_pll < 8 * MHZ)  in exynos_mipi_dsi_change_pll()
293 		else if (dfin_pll < 9 * MHZ)  in exynos_mipi_dsi_change_pll()
295 		else if (dfin_pll < 10 * MHZ)  in exynos_mipi_dsi_change_pll()
297 		else if (dfin_pll < 11 * MHZ)  in exynos_mipi_dsi_change_pll()
314 		if (dpll_out < dpll_table[i] * MHZ) {  in exynos_mipi_dsi_change_pll()
336 		(dpll_out / MHZ));  in exynos_mipi_dsi_change_pll()
377 		if ((byte_clk / esc_div) >= (20 * MHZ) ||  in exynos_mipi_dsi_set_clock()
395 			(byte_clk / MHZ));  in exynos_mipi_dsi_set_clock()
397 			(dsim->dsim_config->esc_clk / MHZ));  in exynos_mipi_dsi_set_clock()
400 			((byte_clk / esc_div) / MHZ));  in exynos_mipi_dsi_set_clock()