183d92566SShaohui Xie#PBI commands 283d92566SShaohui Xie#Initialize CPC1 383d92566SShaohui Xie09010000 00200400 483d92566SShaohui Xie09138000 00000000 583d92566SShaohui Xie091380c0 00000100 683d92566SShaohui Xie#Configure CPC1 as 512KB SRAM 783d92566SShaohui Xie09010100 00000000 883d92566SShaohui Xie09010104 fff80009 983d92566SShaohui Xie09010f00 08000000 1083d92566SShaohui Xie09010000 80000000 1183d92566SShaohui Xie#Configure LAW for CPC1 1283d92566SShaohui Xie09000d00 00000000 1383d92566SShaohui Xie09000d04 fff80000 1483d92566SShaohui Xie09000d08 81000012 1583d92566SShaohui Xie#Configure alternate space 1683d92566SShaohui Xie09000010 00000000 1783d92566SShaohui Xie09000014 ff000000 1883d92566SShaohui Xie09000018 81000000 1983d92566SShaohui Xie#Configure SPI controller 2083d92566SShaohui Xie09110000 80000403 2183d92566SShaohui Xie09110020 2d170008 2283d92566SShaohui Xie09110024 00100008 2383d92566SShaohui Xie09110028 00100008 2483d92566SShaohui Xie0911002c 00100008 25*6b50f62cSPrabhakar Kushwaha#slowing down the MDC clock to make it <= 2.5 MHZ 26*6b50f62cSPrabhakar Kushwaha094fc030 00008148 27*6b50f62cSPrabhakar Kushwaha094fd030 00008148 2883d92566SShaohui Xie#Flush PBL data 2983d92566SShaohui Xie09138000 00000000 3083d92566SShaohui Xie091380c0 00000000 31