Searched refs:HPLL (Results 1 – 11 of 11) sorted by relevance
| /rk3399_rockchip-uboot/arch/arm/mach-s5pc1xx/include/mach/ |
| H A D | clk.h | 15 #define HPLL 3 macro
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| /rk3399_rockchip-uboot/arch/arm/mach-exynos/include/mach/ |
| H A D | clk.h | 14 #define HPLL 3 macro
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| /rk3399_rockchip-uboot/board/samsung/smdkc100/ |
| H A D | lowlevel_init.S | 105 ldr r1, =0x1111 @ A, M, E, HPLL Muxing
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| /rk3399_rockchip-uboot/drivers/clk/rockchip/ |
| H A D | clk_rk3562.c | 53 [HPLL] = PLL(pll_rk3328, PLL_HPLL, RK3562_PLL_CON(40),
1380 rate = rockchip_pll_get_rate(&rk3562_pll_clks[HPLL], priv->cru, in rk3562_clk_get_rate()
1381 HPLL); in rk3562_clk_get_rate()
1510 ret = rockchip_pll_set_rate(&rk3562_pll_clks[HPLL], priv->cru, in rk3562_clk_set_rate()
1511 HPLL, rate); in rk3562_clk_set_rate()
1512 priv->hpll_hz = rockchip_pll_get_rate(&rk3562_pll_clks[HPLL], in rk3562_clk_set_rate()
1513 priv->cru, HPLL); in rk3562_clk_set_rate()
1838 ret = rockchip_pll_set_rate(&rk3562_pll_clks[HPLL], priv->cru, in rk3562_clk_init()
1839 HPLL, HPLL_HZ); in rk3562_clk_init()
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| H A D | clk_rk3568.c | 82 [HPLL] = PLL(pll_rk3328, PLL_HPLL, RK3568_PMU_PLL_CON(16),
386 rate = rockchip_pll_get_rate(&rk3568_pll_clks[HPLL], in rk3568_pmuclk_get_rate()
387 priv->pmucru, HPLL); in rk3568_pmuclk_get_rate()
428 ret = rockchip_pll_set_rate(&rk3568_pll_clks[HPLL], in rk3568_pmuclk_set_rate()
429 priv->pmucru, HPLL, rate); in rk3568_pmuclk_set_rate()
430 priv->hpll_hz = rockchip_pll_get_rate(&rk3568_pll_clks[HPLL], in rk3568_pmuclk_set_rate()
431 priv->pmucru, HPLL); in rk3568_pmuclk_set_rate()
1804 parent = rk3568_pmu_pll_get_rate(priv, HPLL); in rk3568_dclk_vop_get_clk()
1850 rk3568_pmu_pll_set_rate(priv, HPLL, div * rate); in rk3568_dclk_vop_set_clk()
1921 return rk3568_pmu_pll_get_rate(priv, HPLL); in rk3568_gmac_src_get_clk()
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| H A D | clk_rv1126.c | 66 [HPLL] = PLL(pll_rk3328, PLL_HPLL, RV1126_PLL_CON(24),
1633 rate = rockchip_pll_get_rate(&rv1126_pll_clks[HPLL], priv->cru, in rv1126_clk_get_rate()
1634 HPLL); in rv1126_clk_get_rate()
1755 ret = rockchip_pll_set_rate(&rv1126_pll_clks[HPLL], priv->cru, in rv1126_clk_set_rate()
1756 HPLL, rate); in rv1126_clk_set_rate()
2153 ret = rockchip_pll_set_rate(&rv1126_pll_clks[HPLL], priv->cru, in rv1126_clk_init()
2154 HPLL, HPLL_HZ); in rv1126_clk_init()
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| /rk3399_rockchip-uboot/arch/arm/mach-s5pc1xx/ |
| H A D | clock.c | 43 case HPLL: in s5pc100_get_pll_clk()
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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/ |
| H A D | cru_rv1126.h | 51 HPLL, enumerator
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| H A D | cru_rk3562.h | 27 HPLL, enumerator
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| H A D | cru_rk3568.h | 28 HPLL, enumerator
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| /rk3399_rockchip-uboot/board/samsung/goni/ |
| H A D | lowlevel_init.S | 285 ldr r1, =0x00001111 @ A, M, E, HPLL Muxing
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