| /rk3399_ARM-atf/fdts/ |
| H A D | stm32mp21xf.dtsi | 13 resets = <&rcc CRYP1_R>; 21 resets = <&rcc CRYP2_R>; 29 resets = <&rcc SAES_R>; 37 resets = <&rcc PKA_R>;
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| H A D | stm32mp21xc.dtsi | 13 resets = <&rcc CRYP1_R>; 21 resets = <&rcc CRYP2_R>; 29 resets = <&rcc SAES_R>; 37 resets = <&rcc PKA_R>;
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| H A D | stm32mp23xf.dtsi | 13 resets = <&rcc CRYP1_R>; 21 resets = <&rcc CRYP2_R>; 29 resets = <&rcc SAES_R>; 37 resets = <&rcc PKA_R>;
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| H A D | stm32mp23xc.dtsi | 13 resets = <&rcc CRYP1_R>; 21 resets = <&rcc CRYP2_R>; 29 resets = <&rcc SAES_R>; 37 resets = <&rcc PKA_R>;
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| H A D | stm32mp251.dtsi | 9 #include <dt-bindings/reset/stm32mp25-resets.h> 97 resets = <&rcc USART2_R>; 105 resets = <&rcc USART3_R>; 113 resets = <&rcc UART4_R>; 121 resets = <&rcc UART5_R>; 129 resets = <&rcc I2C1_R>; 137 resets = <&rcc I2C2_R>; 145 resets = <&rcc I2C3_R>; 153 resets = <&rcc I2C4_R>; 161 resets = <&rcc I2C5_R>; [all …]
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| H A D | stm32mp131.dtsi | 8 #include <dt-bindings/reset/stm32mp13-resets.h> 86 resets = <&rcc USART3_R>; 95 resets = <&rcc UART4_R>; 104 resets = <&rcc UART5_R>; 113 resets = <&rcc UART7_R>; 122 resets = <&rcc UART8_R>; 131 resets = <&rcc USART6_R>; 140 resets = <&rcc USBO_R>; 156 resets = <&rcc USART1_R>; 165 resets = <&rcc USART2_R>; [all …]
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| H A D | stm32mp231.dtsi | 9 #include <dt-bindings/reset/stm32mp25-resets.h> 131 resets = <&rcc OSPIIOM_R>; 141 resets = <&rcc OSPI1_R>, <&rcc OSPI1DLL_R>; 149 resets = <&rcc OSPI2_R>, <&rcc OSPI2DLL_R>; 164 resets = <&rcc USART2_R>; 172 resets = <&rcc USART3_R>; 180 resets = <&rcc UART4_R>; 188 resets = <&rcc UART5_R>; 196 resets = <&rcc I2C1_R>; 204 resets = <&rcc I2C2_R>; [all …]
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| H A D | stm32mp151.dtsi | 8 #include <dt-bindings/reset/stm32mp1-resets.h> 94 resets = <&rcc USART2_R>; 103 resets = <&rcc USART3_R>; 112 resets = <&rcc UART4_R>; 122 resets = <&rcc UART5_R>; 133 resets = <&rcc I2C2_R>; 146 resets = <&rcc UART7_R>; 155 resets = <&rcc UART8_R>; 164 resets = <&rcc USART6_R>; 183 resets = <&rcc USBO_R>; [all …]
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| H A D | stm32mp211.dtsi | 132 resets = <&rcc USART2_R>; 140 resets = <&rcc USART3_R>; 148 resets = <&rcc UART4_R>; 156 resets = <&rcc UART5_R>; 164 resets = <&rcc I2C1_R>; 172 resets = <&rcc I2C2_R>; 180 resets = <&rcc USART6_R>; 188 resets = <&rcc USART1_R>; 196 resets = <&rcc UART7_R>; 204 resets = <&rcc HASH1_R>; [all …]
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| H A D | stm32mp13xf.dtsi | 14 resets = <&rcc SAES_R>; 22 resets = <&rcc PKA_R>;
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| H A D | stm32mp13xc.dtsi | 15 resets = <&rcc SAES_R>; 23 resets = <&rcc PKA_R>;
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| H A D | stm32mp15xc.dtsi | 14 resets = <&rcc CRYP1_R>;
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| /rk3399_ARM-atf/drivers/ti/ti_sci/ |
| H A D | ti_sci_protocol.h | 241 uint32_t resets; member 265 uint32_t resets; member
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| H A D | ti_sci.c | 344 uint32_t *resets, uint8_t *p_state, in ti_sci_device_get_state() argument 353 if (!clcnt && !resets && !p_state && !c_state) in ti_sci_device_get_state() 375 if (resets) in ti_sci_device_get_state() 376 *resets = resp.resets; in ti_sci_device_get_state() 682 req.resets = reset_state; in ti_sci_device_set_resets()
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| /rk3399_ARM-atf/docs/plat/ |
| H A D | ti-k3low-am62lx.rst | 9 loader configures and initializes the DDR4/LPDDR4 subsystem and resets back to the
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| H A D | rz-g2.rst | 71 reference tree [1] resets into EL1 before entering BL2 - see its
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| H A D | rcar-gen3.rst | 71 reference tree [1] resets into EL1 before entering BL2 - see its
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| /rk3399_ARM-atf/docs/security_advisories/ |
| H A D | security-advisory-tfv-5.rst | 48 here ``PMCR_EL0.DP`` architecturally resets to zero.
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| /rk3399_ARM-atf/docs/plat/st/ |
| H A D | stm32mpus.rst | 11 The STM32 MPU resets in the ROM code of the Cortex-A.
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| /rk3399_ARM-atf/docs/design/ |
| H A D | reset-design.rst | 5 resets in Trusted Firmware-A (TF-A). It also describes how the platform 144 In this configuration, since the CPU resets to BL31, no parameters are expected
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| /rk3399_ARM-atf/docs/process/ |
| H A D | security-hardening.rst | 95 - ``MDCR_EL3.SPME`` resets to ``0``, so by default general events should
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| H A D | coding-guidelines.rst | 302 it may set a flag so the platform resets into a different mode). Also,
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| /rk3399_ARM-atf/docs/ |
| H A D | porting-guide.rst | 1272 resets while booting from the active bank, the platform can then switch to boot 3307 resets, all failures must return ``PSCI_E_INVALID_PARAMETERS``
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| H A D | change-log.md | 12638 - The version of the AEMv8 Base FVP used in this release resets the model 12773 - The version of the AEMv8 Base FVP used in this release resets the model 12911 - The version of the AEMv8 Base FVP used in this release resets the model
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