| #
6c0c3a74 |
| 06-Apr-2026 |
Govindraj Raja <govindraj.raja@arm.com> |
Merge changes from topic "am62l-bl1" into integration
* changes:
feat(k3low): add BL1 platform definitions and integration for AM62L
feat(k3low): add AM62L DDR platform shim and EVM board config
Merge changes from topic "am62l-bl1" into integration
* changes:
feat(k3low): add BL1 platform definitions and integration for AM62L
feat(k3low): add AM62L DDR platform shim and EVM board config
feat(k3low): introduce Cadence LPDDR4 core driver for AM62L
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| #
5421f84b |
| 25-Mar-2026 |
Hari Nagalla <hnagalla@ti.com> |
feat(k3low): introduce Cadence LPDDR4 core driver for AM62L
AM62L devices support 16-bit DDR4/LPDDR4 DRAM memory devices. The core
DDR4/LPDDR4 driver was developed by Cadence. This patch introduces
feat(k3low): introduce Cadence LPDDR4 core driver for AM62L
AM62L devices support 16-bit DDR4/LPDDR4 DRAM memory devices. The core
DDR4/LPDDR4 driver was developed by Cadence. This patch introduces the
Cadence IP driver files (lpddr4.c, lpddr4_16bit.c, lpddr4_obj_if.c and
their associated headers) which carry dual copyright (Cadence + TI).
The driver was pruned from ~6800 macros to ~80 with AI-assisted removal
of unused code; the Cadence CTL/PHY/PI API surface remains intact for
review against the User Guides.
These files are intentionally unreferenced in platform.mk pending the
AM62L platform shim in the next patch.
For additional information please check the technical reference
manual at:
https://www.ti.com/lit/pdf/sprujb4
Change-Id: I8b02a6b30e5ea7b1b457cc0a933d8ef232993fa1
Co-developed-by: Claude <noreply@anthropic.com>
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
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