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Searched refs:mmio_read_32 (Results 1 – 25 of 588) sorted by relevance

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/rk3399_ARM-atf/plat/hisilicon/hikey/
H A Dhikey_ddr.c24 data = mmio_read_32((0xf7032000 + 0x000)); in init_pll()
28 data = mmio_read_32((0xf7032000 + 0x000)); in init_pll()
31 data = mmio_read_32((0xf7800000 + 0x000)); in init_pll()
36 data = mmio_read_32((0xf7800000 + 0x014)); in init_pll()
56 data = mmio_read_32(0xf7032000 + 0x050); in init_pll()
90 data = mmio_read_32((0xf7032000 + 0x110)); in init_freq()
94 data = mmio_read_32((0xf7032000 + 0x110)); in init_freq()
99 data = mmio_read_32((0xf7032000 + 0x110)); in init_freq()
108 data = mmio_read_32((0xf6504000 + 0x008)); in init_freq()
115 data = mmio_read_32((0xf6504000 + 0x054)); in init_freq()
[all …]
H A Dhikey_bl_common.c22 data = mmio_read_32(AO_SC_TIMER_EN0); in hikey_sp804_init()
27 data = mmio_read_32(AO_SC_TIMER_EN0); in hikey_sp804_init()
30 data = mmio_read_32(AO_SC_PERIPH_CLKSTAT4); in hikey_sp804_init()
33 data = mmio_read_32(AO_SC_PERIPH_CLKSTAT4); in hikey_sp804_init()
36 data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4); in hikey_sp804_init()
39 data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4); in hikey_sp804_init()
44 data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4); in hikey_sp804_init()
98 data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4); in hikey_pmussi_init()
102 data = mmio_read_32(AO_SC_MCU_SUBSYS_CTRL3); in hikey_pmussi_init()
221 data = mmio_read_32(PERI_SC_CLK_SEL0); in init_mmc0_pll()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3368/drivers/ddr/
H A Dddr_rk3368.c207 fb_div = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEC); in ddr_get_phy_pll_freq()
208 fb_div |= (mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGED) & 0x1) << 8; in ddr_get_phy_pll_freq()
210 pre_div = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEE) & 0xff; in ddr_get_phy_pll_freq()
260 pctl_tim->SCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_SCFG); in ddr_reg_save()
261 pctl_tim->CMDTSTATEN = mmio_read_32(DDR_PCTL_BASE + in ddr_reg_save()
263 pctl_tim->MCFG1 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_MCFG1); in ddr_reg_save()
264 pctl_tim->MCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_MCFG); in ddr_reg_save()
265 pctl_tim->PPCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_PPCFG); in ddr_reg_save()
266 pctl_tim->pctl_timing.ddrfreq = mmio_read_32(DDR_PCTL_BASE + in ddr_reg_save()
268 pctl_tim->DFITCTRLDELAY = mmio_read_32(DDR_PCTL_BASE + in ddr_reg_save()
[all …]
/rk3399_ARM-atf/plat/imx/imx8m/ddr/
H A Dlpddr4_dvfs.c18 while (mmio_read_32(DDRC_MRSTAT(0)) & 0x1) in lpddr4_mr_write()
61 phy_master = mmio_read_32(DDRC_DFIPHYMSTR(0)); in lpddr4_swffc()
76 val = mmio_read_32(DDRC_MRSTAT(0)); in lpddr4_swffc()
84 val = mmio_read_32(DDRC_PSTAT(0)); in lpddr4_swffc()
93 val = mmio_read_32(DDRC_DFILPCFG0(0)); in lpddr4_swffc()
97 val = mmio_read_32(DDRC_DFISTAT(0)); // dfi_lp_ack in lpddr4_swffc()
98 val2 = mmio_read_32(DDRC_STAT(0)); // operating_mode in lpddr4_swffc()
105 val = mmio_read_32(DDRC_STAT(0)); in lpddr4_swffc()
109 val = mmio_read_32(DDRC_DERATEEN(0)); in lpddr4_swffc()
113 val = mmio_read_32(DDRC_FREQ1_DERATEEN(0)); in lpddr4_swffc()
[all …]
H A Dddr4_dvfs.c33 while (mmio_read_32(DDRC_MRSTAT(0)) & 0x1) { in ddr4_mr_write()
37 } while (mmio_read_32(DDRC_MRSTAT(0)) & 0x1); in ddr4_mr_write()
43 val = mmio_read_32(DDRC_DIMMCTL(0)); in ddr4_mr_write()
72 while (mmio_read_32(DDRC_MRSTAT(0))) { in ddr4_mr_write()
113 val = mmio_read_32(DDRC_RFSHCTL3(0)); in sw_pstate()
130 while (mmio_read_32(DDRC_DFISTAT(0)) & 0x1) { in sw_pstate()
140 while (!(mmio_read_32(DDRC_DFISTAT(0)) & 0x1)) { in sw_pstate()
156 while ((mmio_read_32(DDRC_STAT(0)) & 0x3f) == 0x23) { in sw_pstate()
182 while (mmio_read_32(DDRC_PSTAT(0)) & 0x10001) { in ddr4_swffc()
201 while ((mmio_read_32(DDRC_DBGCAM(0)) & 0x06000000) != 0x06000000) { in ddr4_swffc()
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spm/
H A Dmt_spm_internal.c118 wakesta->clk_settle, mmio_read_32(SYS_TIMER_VALUE_L), in __spm_output_wake_reason()
119 mmio_read_32(SYS_TIMER_VALUE_H)); in __spm_output_wake_reason()
122 bk_vtcxo_dur = mmio_read_32(SPM_BK_VTCXO_DUR); in __spm_output_wake_reason()
385 wakesta->tr.comm.r12 = mmio_read_32(SPM_BK_WAKE_EVENT); in __spm_get_wakeup_status()
386 wakesta->tr.comm.timer_out = mmio_read_32(SPM_BK_PCM_TIMER); in __spm_get_wakeup_status()
387 wakesta->tr.comm.r13 = mmio_read_32(PCM_REG13_DATA); in __spm_get_wakeup_status()
388 wakesta->tr.comm.req_sta0 = mmio_read_32(SRC_REQ_STA_0); in __spm_get_wakeup_status()
389 wakesta->tr.comm.req_sta1 = mmio_read_32(SRC_REQ_STA_1); in __spm_get_wakeup_status()
390 wakesta->tr.comm.req_sta2 = mmio_read_32(SRC_REQ_STA_2); in __spm_get_wakeup_status()
391 wakesta->tr.comm.req_sta3 = mmio_read_32(SRC_REQ_STA_3); in __spm_get_wakeup_status()
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8183/drivers/mcsi/
H A Dmcsi.c46 if ((mmio_read_32(cci_base_addr + FLUSH_SF) & 0x1) == 0x0) in mcsi_cache_flush()
85 support_ability = mmio_read_32(slave_base); in cci_enable_cluster_coherency()
87 pending = (mmio_read_32( in cci_enable_cluster_coherency()
90 pending = (mmio_read_32( in cci_enable_cluster_coherency()
102 while (mmio_read_32(cci_base_addr + SNP_PENDING_REG) >> SNP_PENDING) in cci_enable_cluster_coherency()
118 while (mmio_read_32(cci_base_addr + SNP_PENDING_REG) >> SNP_PENDING) in cci_disable_cluster_coherency()
121 config = mmio_read_32(slave_base); in cci_disable_cluster_coherency()
132 while (mmio_read_32(cci_base_addr + SNP_PENDING_REG) >> SNP_PENDING) in cci_disable_cluster_coherency()
140 config = mmio_read_32(cci_base_addr + CENTRAL_CTRL_REG); in cci_secure_switch()
152 config = mmio_read_32(cci_base_addr + CENTRAL_CTRL_REG); in cci_pmu_secure_switch()
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spm/
H A Dmt_spm_internal.c111 wakesta->clk_settle, mmio_read_32(SYS_TIMER_VALUE_L), in __spm_output_wake_reason()
112 mmio_read_32(SYS_TIMER_VALUE_H)); in __spm_output_wake_reason()
115 bk_vtcxo_dur = mmio_read_32(SPM_BK_VTCXO_DUR); in __spm_output_wake_reason()
423 wakesta->tr.comm.r12 = mmio_read_32(SPM_BK_WAKE_EVENT); in __spm_get_wakeup_status()
424 wakesta->tr.comm.timer_out = mmio_read_32(SPM_BK_PCM_TIMER); in __spm_get_wakeup_status()
425 wakesta->tr.comm.r13 = mmio_read_32(PCM_REG13_DATA); in __spm_get_wakeup_status()
426 wakesta->tr.comm.req_sta0 = mmio_read_32(SRC_REQ_STA_0); in __spm_get_wakeup_status()
427 wakesta->tr.comm.req_sta1 = mmio_read_32(SRC_REQ_STA_1); in __spm_get_wakeup_status()
428 wakesta->tr.comm.req_sta2 = mmio_read_32(SRC_REQ_STA_2); in __spm_get_wakeup_status()
429 wakesta->tr.comm.req_sta3 = mmio_read_32(SRC_REQ_STA_3); in __spm_get_wakeup_status()
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/
H A Dmt_spm_internal.c100 wakesta->clk_settle, mmio_read_32(SYS_TIMER_VALUE_L), in __spm_output_wake_reason()
101 mmio_read_32(SYS_TIMER_VALUE_H)); in __spm_output_wake_reason()
104 bk_vtcxo_dur = mmio_read_32(SPM_BK_VTCXO_DUR); in __spm_output_wake_reason()
457 wakesta->tr.comm.r12 = mmio_read_32(SPM_BK_WAKE_EVENT); in __spm_get_wakeup_status()
458 wakesta->tr.comm.timer_out = mmio_read_32(SPM_BK_PCM_TIMER); in __spm_get_wakeup_status()
459 wakesta->tr.comm.r13 = mmio_read_32(PCM_REG13_DATA); in __spm_get_wakeup_status()
460 wakesta->tr.comm.req_sta0 = mmio_read_32(SRC_REQ_STA_0); in __spm_get_wakeup_status()
461 wakesta->tr.comm.req_sta1 = mmio_read_32(SRC_REQ_STA_1); in __spm_get_wakeup_status()
462 wakesta->tr.comm.req_sta2 = mmio_read_32(SRC_REQ_STA_2); in __spm_get_wakeup_status()
463 wakesta->tr.comm.req_sta3 = mmio_read_32(SRC_REQ_STA_3); in __spm_get_wakeup_status()
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/vcp/rv/
H A Dmmup_common.c20 if (mmio_read_32(VCP_GPR_CORE1_REBOOT) != 0 && in mmup_smc_rstn_set()
21 mmio_read_32(VCP_R_CORE1_STATUS) != 0 && in mmup_smc_rstn_set()
22 (mmio_read_32(VCP_R_GIPC_IN_SET) & B_GIPC3_SETCLR_1) == 0 && in mmup_smc_rstn_set()
23 (mmio_read_32(VCP_R_GIPC_IN_CLR) & B_GIPC3_SETCLR_1) == 0 && in mmup_smc_rstn_set()
24 mmio_read_32(VCP_GPR_CORE1_REBOOT) != VCP_CORE_RDY_TO_REBOOT) { in mmup_smc_rstn_set()
26 MODULE_TAG, __func__, mmio_read_32(VCP_R_GIPC_IN_SET), in mmup_smc_rstn_set()
27 mmio_read_32(VCP_R_GIPC_IN_CLR), in mmup_smc_rstn_set()
28 mmio_read_32(VCP_GPR_CORE1_REBOOT)); in mmup_smc_rstn_set()
56 if ((mmio_read_32(VCP_R_CORE1_SW_RSTN_SET) & BIT(0)) == 1) { in mmup_smc_rstn_clr()
/rk3399_ARM-atf/plat/mediatek/mt8183/
H A Dplat_debug.c18 mmio_read_32(CA15M_DBG_CONTROL) & ~(BIT_CA15M_LASTPC_DIS)); in circular_buffer_setup()
26 sync_writel(VPROC_EXT_CTL, mmio_read_32(VPROC_EXT_CTL) & ~(0x1 << 1)); in circular_buffer_unlock()
29 sync_writel(CA15M_PWR_RST_CTL, mmio_read_32(CA15M_PWR_RST_CTL) & ~(0x1 << 1)); in circular_buffer_unlock()
33 (mmio_read_32(MP1_CPUTOP_PWR_CON + i * 4) & ~(0x4))|(0x4)); in circular_buffer_unlock()
48 mmio_read_32(MCU_ALL_PWR_ON_CTRL) & ~(1 << 2)); in clear_all_on_mux()
50 mmio_read_32(MCU_ALL_PWR_ON_CTRL) & ~(1 << 1)); in clear_all_on_mux()
57 mmio_read_32(CA15M_DBG_CONTROL) | BIT_CA15M_L2PARITY_EN); in l2c_parity_check_setup()
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/apusys/
H A Dmtk_apusys.c48 mmio_read_32(REVISER_SECUREFW_CTXT), in apusys_kernel_ctrl()
49 mmio_read_32(REVISER_USDRFW_CTXT)); in apusys_kernel_ctrl()
51 mmio_read_32(AO_SEC_FW), in apusys_kernel_ctrl()
52 mmio_read_32(AO_SEC_USR_FW), in apusys_kernel_ctrl()
53 mmio_read_32(AO_MD32_BOOT_CTRL), in apusys_kernel_ctrl()
54 mmio_read_32(AO_MD32_PRE_DEFINE), in apusys_kernel_ctrl()
55 mmio_read_32(AO_MD32_SYS_CTRL)); in apusys_kernel_ctrl()
62 mmio_read_32(AO_MD32_BOOT_CTRL), in apusys_kernel_ctrl()
63 mmio_read_32(AO_MD32_SYS_CTRL)); in apusys_kernel_ctrl()
/rk3399_ARM-atf/plat/arm/common/
H A Darm_ni.c79 subfeature_count = mmio_read_32(comp_addr + NI_COMP_NUM_SUBFEATURES); in ni_enable_fcu_ns_access()
82 NI_NODE_TYPE(mmio_read_32(comp_addr + NI_COMP_SUBFEATURE_TYPE(i))); in ni_enable_fcu_ns_access()
101 node_info = mmio_read_32(comp_addr); in ni_setup_component()
133 reg = mmio_read_32(global_cfg + NI_PERIPHERAL_ID0); in plat_arm_ni_setup()
135 reg = mmio_read_32(global_cfg + NI_PERIPHERAL_ID1); in plat_arm_ni_setup()
143 vd_count = mmio_read_32(global_cfg + NI_CHILD_NODE_COUNT); in plat_arm_ni_setup()
146 vd_addr = global_cfg + mmio_read_32(global_cfg + NI_CHILD_POINTER(i)); in plat_arm_ni_setup()
149 i, vd_addr, mmio_read_32(vd_addr)); in plat_arm_ni_setup()
151 pd_count = mmio_read_32(vd_addr + NI_CHILD_NODE_COUNT); in plat_arm_ni_setup()
154 pd_addr = global_cfg + mmio_read_32(vd_addr + NI_CHILD_POINTER(j)); in plat_arm_ni_setup()
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/apusys/
H A Dmtk_apusys.c46 mmio_read_32(REVISER_SECUREFW_CTXT), in apusys_kernel_ctrl()
47 mmio_read_32(REVISER_USDRFW_CTXT)); in apusys_kernel_ctrl()
49 mmio_read_32(AO_SEC_FW), in apusys_kernel_ctrl()
50 mmio_read_32(AO_MD32_BOOT_CTRL), in apusys_kernel_ctrl()
51 mmio_read_32(AO_MD32_PRE_DEFINE), in apusys_kernel_ctrl()
52 mmio_read_32(AO_MD32_SYS_CTRL)); in apusys_kernel_ctrl()
59 mmio_read_32(AO_MD32_BOOT_CTRL), in apusys_kernel_ctrl()
60 mmio_read_32(AO_MD32_SYS_CTRL)); in apusys_kernel_ctrl()
/rk3399_ARM-atf/plat/imx/imx8ulp/
H A Dapd_context.c168 iomuxc_ctx[index++] = mmio_read_32(iomuxc_sections[i].offset + j * 4); in iomuxc_save()
195 ctx->port_ctrl[j] = mmio_read_32(ctx->base + gpio_ctrl_offset[j]); in gpio_save()
202 ctx->port_ctrl[j] = mmio_read_32(ctx->base + gpio_ctrl_offset[j]); in gpio_save()
207 ctx->gpio_icr[j] = mmio_read_32(ctx->base + 0x80 + j * 4); in gpio_save()
241 pll2[i][1] = mmio_read_32(pll2[i][0]); in cgc1_save()
246 pll3[i][1] = mmio_read_32(pll3[i][0]); in cgc1_save()
251 cgc1[i][1] = mmio_read_32(cgc1[i][0]); in cgc1_save()
264 while (!(mmio_read_32(pll2[4][0]) & BIT(24))) { in cgc1_restore()
274 while (!(mmio_read_32(pll3[4][0]) & BIT(24))) { in cgc1_restore()
283 while (!(mmio_read_32(pll3[9][0]) & PFD_VALID_MASK)) { in cgc1_restore()
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8188/
H A Dmt_spm_internal.c68 wakesta->clk_settle, mmio_read_32(SYS_TIMER_VALUE_L), in __spm_output_wake_reason()
69 mmio_read_32(SYS_TIMER_VALUE_H)); in __spm_output_wake_reason()
72 bk_vtcxo_dur = mmio_read_32(SPM_BK_VTCXO_DUR); in __spm_output_wake_reason()
327 wakesta->tr.comm.r12 = mmio_read_32(SPM_BK_WAKE_EVENT); /* backup of PCM_REG12_DATA */ in __spm_get_wakeup_status()
328 wakesta->r12_ext = mmio_read_32(SPM_WAKEUP_EXT_STA); in __spm_get_wakeup_status()
329 wakesta->tr.comm.raw_sta = mmio_read_32(SPM_WAKEUP_STA); in __spm_get_wakeup_status()
330 wakesta->raw_ext_sta = mmio_read_32(SPM_WAKEUP_EXT_STA); in __spm_get_wakeup_status()
331 wakesta->md32pcm_wakeup_sta = mmio_read_32(MD32PCM_WAKEUP_STA); in __spm_get_wakeup_status()
332 wakesta->md32pcm_event_sta = mmio_read_32(MD32PCM_EVENT_STA); in __spm_get_wakeup_status()
333 wakesta->wake_misc = mmio_read_32(SPM_BK_WAKE_MISC); /* backup of SPM_WAKEUP_MISC */ in __spm_get_wakeup_status()
[all …]
/rk3399_ARM-atf/drivers/renesas/common/ddr/ddr_a/
H A Dddr_init_d3.c70 while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) in init_ddr_d3_1866()
90 while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) in init_ddr_d3_1866()
98 while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) in init_ddr_d3_1866()
104 while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(30))) in init_ddr_d3_1866()
138 while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) in init_ddr_d3_1866()
155 r2 = (mmio_read_32(DBSC_DBPDRGD_0) & 0x0000FF00) >> 0x9; in init_ddr_d3_1866()
175 while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) in init_ddr_d3_1866()
181 while (!(mmio_read_32(DBSC_DBPDRGD_0) & BIT(0))) in init_ddr_d3_1866()
186 r5 = (mmio_read_32(DBSC_DBPDRGD_0) & 0xFF00) >> 0x8; in init_ddr_d3_1866()
188 r6 = mmio_read_32(DBSC_DBPDRGD_0) & 0xFF; in init_ddr_d3_1866()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/m0/src/
H A Ddram.c18 gatedis_con0 = mmio_read_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0); in idle_port()
23 while ((mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & in idle_port()
33 while (mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & in deidle_port()
47 mmio_read_32(PARAM_ADDR + PARAM_DPLL_CON0)); in ddr_set_pll()
49 mmio_read_32(PARAM_ADDR + PARAM_DPLL_CON1)); in ddr_set_pll()
52 while ((mmio_read_32(CRU_BASE + CRU_DPLL_CON2) & (1u << 31)) == 0) in ddr_set_pll()
67 mmio_read_32(PARAM_ADDR + PARAM_FREQ_SELECT)); in m0_main()
68 while ((mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 2)) == 0) in m0_main()
73 while ((mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 0)) == 0) in m0_main()
/rk3399_ARM-atf/plat/mediatek/drivers/audio/mt8188/
H A Daudio_domain.c20 uint32_t val = mmio_read_32(PWR_STATUS); in set_audio_domain_sidebands()
37 mmio_read_32(AFE_SE_SECURE_CON), in set_audio_domain_sidebands()
38 mmio_read_32(AFE_SECURE_SIDEBAND0), in set_audio_domain_sidebands()
39 mmio_read_32(AFE_SECURE_SIDEBAND1), in set_audio_domain_sidebands()
40 mmio_read_32(AFE_SECURE_SIDEBAND2), in set_audio_domain_sidebands()
41 mmio_read_32(AFE_SECURE_SIDEBAND3)); in set_audio_domain_sidebands()
/rk3399_ARM-atf/plat/mediatek/drivers/uart/
H A Duart.c70 uart->registers.lcr = mmio_read_32(UART_LCR(base)); in mt_uart_save()
73 uart->registers.efr = mmio_read_32(UART_EFR(base)); in mt_uart_save()
75 uart->registers.fcr = mmio_read_32(UART_FCR_RD(base)); in mt_uart_save()
78 uart->registers.highspeed = mmio_read_32(UART_HIGHSPEED(base)); in mt_uart_save()
79 uart->registers.fracdiv_l = mmio_read_32(UART_FRACDIV_L(base)); in mt_uart_save()
80 uart->registers.fracdiv_m = mmio_read_32(UART_FRACDIV_M(base)); in mt_uart_save()
83 uart->registers.dll = mmio_read_32(UART_DLL(base)); in mt_uart_save()
84 uart->registers.dlh = mmio_read_32(UART_DLH(base)); in mt_uart_save()
86 uart->registers.sample_count = mmio_read_32( in mt_uart_save()
88 uart->registers.sample_point = mmio_read_32( in mt_uart_save()
[all …]
/rk3399_ARM-atf/plat/marvell/armada/a8k/common/
H A Dplat_pm_trace.c37 mmio_read_32(AP_MSS_ATF_CORE_0_CTRL_BASE); in pm_core_0_trace()
40 mmio_read_32(AP_MSS_TIMER_BASE)); in pm_core_0_trace()
52 mmio_read_32(AP_MSS_ATF_CORE_1_CTRL_BASE); in pm_core_1_trace()
55 mmio_read_32(AP_MSS_TIMER_BASE)); in pm_core_1_trace()
67 mmio_read_32(AP_MSS_ATF_CORE_2_CTRL_BASE); in pm_core_2_trace()
70 mmio_read_32(AP_MSS_TIMER_BASE)); in pm_core_2_trace()
82 mmio_read_32(AP_MSS_ATF_CORE_3_CTRL_BASE); in pm_core_3_trace()
85 mmio_read_32(AP_MSS_TIMER_BASE)); in pm_core_3_trace()
/rk3399_ARM-atf/drivers/rpi3/sdhost/
H A Drpi3_sdhost.c54 while ((mmio_read_32(reg_base + HC_COMMAND) & HC_CMD_ENABLE) in rpi3_sdhost_waitcommand()
79 status = mmio_read_32(reg_base + HC_HOSTSTATUS); in send_command_raw()
142 while (mmio_read_32(reg_base + HC_HOSTSTATUS) & HC_HSTST_HAVEDATA) { in rpi3_drain_fifo()
143 mmio_read_32(reg_base + HC_DATAPORT); in rpi3_drain_fifo()
150 edm = mmio_read_32(reg_base + HC_DEBUG); in rpi3_drain_fifo()
181 mmio_read_32(reg_base + HC_COMMAND)); in rpi3_sdhost_print_regs()
183 mmio_read_32(reg_base + HC_ARGUMENT)); in rpi3_sdhost_print_regs()
185 mmio_read_32(reg_base + HC_TIMEOUTCOUNTER)); in rpi3_sdhost_print_regs()
187 mmio_read_32(reg_base + HC_CLOCKDIVISOR)); in rpi3_sdhost_print_regs()
189 mmio_read_32(reg_base + HC_RESPONSE_0)); in rpi3_sdhost_print_regs()
[all …]
/rk3399_ARM-atf/plat/intel/soc/agilex5/soc/
H A Dagilex5_memory_controller.c79 hmc_clk = mmio_read_32(AGX_SYSMGR_CORE_HMC_CLK); in check_hmc_clk()
99 data = mmio_read_32(AGX_MPFE_HMC_ADP_RSTHANDSHAKESTAT); in clear_emif()
125 data = mmio_read_32(AGX_MPFE_HMC_ADP_DDRCALSTAT); in mem_calibration()
185 data = mmio_read_32(AGX_MPFE_IOHMC_CTRLCFG1); in configure_ddr_sched_ctrl_regs()
188 data = mmio_read_32(AGX_MPFE_IOHMC_DRAMADDRW); in configure_ddr_sched_ctrl_regs()
208 data = mmio_read_32(AGX_MPFE_IOHMC_DRAMTIMING0); in configure_ddr_sched_ctrl_regs()
211 data = mmio_read_32(AGX_MPFE_IOHMC_CALTIMING0); in configure_ddr_sched_ctrl_regs()
216 data = mmio_read_32(AGX_MPFE_IOHMC_CALTIMING1); in configure_ddr_sched_ctrl_regs()
221 data = mmio_read_32(AGX_MPFE_IOHMC_CALTIMING2); in configure_ddr_sched_ctrl_regs()
224 data = mmio_read_32(AGX_MPFE_IOHMC_CALTIMING3); in configure_ddr_sched_ctrl_regs()
[all …]
/rk3399_ARM-atf/plat/intel/soc/agilex/soc/
H A Dagilex_memory_controller.c78 hmc_clk = mmio_read_32(AGX_SYSMGR_CORE_HMC_CLK); in check_hmc_clk()
98 data = mmio_read_32(AGX_MPFE_HMC_ADP_RSTHANDSHAKESTAT); in clear_emif()
124 data = mmio_read_32(AGX_MPFE_HMC_ADP_DDRCALSTAT); in mem_calibration()
184 data = mmio_read_32(AGX_MPFE_IOHMC_CTRLCFG1); in configure_ddr_sched_ctrl_regs()
187 data = mmio_read_32(AGX_MPFE_IOHMC_DRAMADDRW); in configure_ddr_sched_ctrl_regs()
207 data = mmio_read_32(AGX_MPFE_IOHMC_DRAMTIMING0); in configure_ddr_sched_ctrl_regs()
210 data = mmio_read_32(AGX_MPFE_IOHMC_CALTIMING0); in configure_ddr_sched_ctrl_regs()
215 data = mmio_read_32(AGX_MPFE_IOHMC_CALTIMING1); in configure_ddr_sched_ctrl_regs()
220 data = mmio_read_32(AGX_MPFE_IOHMC_CALTIMING2); in configure_ddr_sched_ctrl_regs()
223 data = mmio_read_32(AGX_MPFE_IOHMC_CALTIMING3); in configure_ddr_sched_ctrl_regs()
[all …]
/rk3399_ARM-atf/drivers/arm/gic/v2/
H A Dgicv2_private.h32 return mmio_read_32(base + GICD_PIDR2_GICV2); in gicd_read_pidr2()
62 return mmio_read_32(base + GICC_CTLR); in gicc_read_ctlr()
67 return mmio_read_32(base + GICC_PMR); in gicc_read_pmr()
72 return mmio_read_32(base + GICC_BPR); in gicc_read_BPR()
77 return mmio_read_32(base + GICC_IAR); in gicc_read_IAR()
82 return mmio_read_32(base + GICC_EOIR); in gicc_read_EOIR()
87 return mmio_read_32(base + GICC_HPPIR); in gicc_read_hppir()
92 return mmio_read_32(base + GICC_AHPPIR); in gicc_read_ahppir()
97 return mmio_read_32(base + GICC_DIR); in gicc_read_dir()
102 return mmio_read_32(base + GICC_IIDR); in gicc_read_iidr()
[all …]

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