168 			iomuxc_ctx[index++] = mmio_read_32(iomuxc_sections[i].offset + j * 4);  in iomuxc_save()
195 				ctx->port_ctrl[j] = mmio_read_32(ctx->base + gpio_ctrl_offset[j]);  in gpio_save()
202 				ctx->port_ctrl[j] = mmio_read_32(ctx->base + gpio_ctrl_offset[j]);  in gpio_save()
207 			ctx->gpio_icr[j] = mmio_read_32(ctx->base + 0x80 + j * 4);  in gpio_save()
241 		pll2[i][1] = mmio_read_32(pll2[i][0]);  in cgc1_save()
246 		pll3[i][1] = mmio_read_32(pll3[i][0]);  in cgc1_save()
251 		cgc1[i][1] = mmio_read_32(cgc1[i][0]);  in cgc1_save()
264 	while (!(mmio_read_32(pll2[4][0]) & BIT(24))) {  in cgc1_restore()
274 	while (!(mmio_read_32(pll3[4][0]) & BIT(24))) {  in cgc1_restore()
283 	while (!(mmio_read_32(pll3[9][0]) & PFD_VALID_MASK)) {  in cgc1_restore()
295 	tpm5[0] = mmio_read_32(IMX_TPM5_BASE + 0x10);  in tpm5_save()
296 	tpm5[1] = mmio_read_32(IMX_TPM5_BASE + 0x18);  in tpm5_save()
297 	tpm5[2] = mmio_read_32(IMX_TPM5_BASE + 0x20);  in tpm5_save()
313 	wdog3[0] = mmio_read_32(IMX_WDOG3_BASE);  in wdog3_save()
314 	wdog3[1] = mmio_read_32(IMX_WDOG3_BASE + 0x8);  in wdog3_save()
328 	while ((mmio_read_32(IMX_WDOG3_BASE) & BIT(11))) {  in wdog3_restore()
333 	while (!(mmio_read_32(IMX_WDOG3_BASE) & BIT(10))) {  in wdog3_restore()
346 	lpuart_regs[0] = mmio_read_32(IMX_LPUART5_BASE + LPUART_BAUD);  in lpuart_save()
347 	lpuart_regs[1] = mmio_read_32(IMX_LPUART5_BASE + LPUART_FIFO);  in lpuart_save()
348 	lpuart_regs[2] = mmio_read_32(IMX_LPUART5_BASE + LPUART_WATER);  in lpuart_save()
349 	lpuart_regs[3] = mmio_read_32(IMX_LPUART5_BASE + LPUART_CTRL);  in lpuart_save()
362 	return (mmio_read_32(0x2802b044) & BIT(7)) ? true : false;  in is_lpav_owned_by_apd()
372 		cgc2[i][1] = mmio_read_32(cgc2[i][0]);  in lpav_ctx_save()
377 		pll4[i][1] = mmio_read_32(pll4[i][0]);  in lpav_ctx_save()
382 		val = mmio_read_32(IMX_PCC5_BASE + i * 4);  in lpav_ctx_save()
389 		val = mmio_read_32(pcc5_1[i][0]);  in lpav_ctx_save()
397 		lpav_sim[i][1] = mmio_read_32(lpav_sim[i][0]);  in lpav_ctx_save()
417 	while (!(mmio_read_32(pll4[8][0]) & BIT(24))) {  in lpav_ctx_restore()
426 	while (!(mmio_read_32(pll4[9][0]) & PFD_VALID_MASK)) {  in lpav_ctx_restore()
469 	cmc1_pmprot = mmio_read_32(IMX_CMC1_BASE + 0x18);  in imx_apd_ctx_save()
470 	cmc1_srie = mmio_read_32(IMX_CMC1_BASE + 0x8c);  in imx_apd_ctx_save()
475 		val = mmio_read_32(IMX_PCC3_BASE + i * 4);  in imx_apd_ctx_save()
484 		val = mmio_read_32(IMX_PCC4_BASE + i * 4);  in imx_apd_ctx_save()
528 		resp = mmio_read_32(S400_MU_RSR);  in s400_release_caam()
531 	msg = mmio_read_32(S400_MU_RRx(0));  in s400_release_caam()
532 	resp = mmio_read_32(S400_MU_RRx(1));  in s400_release_caam()
623 		while (!(mmio_read_32(IMX_SIM1_BASE + DGO_CTRL1) & BIT(1))) {  in usb_wakeup_enable()
636 		while (!(mmio_read_32(IMX_SIM1_BASE + DGO_CTRL1) & BIT(1))) {  in usb_wakeup_enable()
650 		while (!(mmio_read_32(IMX_SIM1_BASE + DGO_CTRL1) & BIT(1))) {  in usb_wakeup_enable()