1 /*
2 * Copyright (c) 2024, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <inttypes.h>
8
9 #include <common/debug.h>
10 #include <lib/mmio.h>
11
12 #include "mmup_common.h"
13 #include "vcp_helper.h"
14 #include "vcp_reg.h"
15
16 #define MODULE_TAG "[MMUP]"
17
mmup_smc_rstn_set(bool boot_ok)18 bool mmup_smc_rstn_set(bool boot_ok)
19 {
20 if (mmio_read_32(VCP_GPR_CORE1_REBOOT) != 0 &&
21 mmio_read_32(VCP_R_CORE1_STATUS) != 0 &&
22 (mmio_read_32(VCP_R_GIPC_IN_SET) & B_GIPC3_SETCLR_1) == 0 &&
23 (mmio_read_32(VCP_R_GIPC_IN_CLR) & B_GIPC3_SETCLR_1) == 0 &&
24 mmio_read_32(VCP_GPR_CORE1_REBOOT) != VCP_CORE_RDY_TO_REBOOT) {
25 ERROR("%s: [%s] mmup reset set fail!GIPC 0x%x 0x%x REBOOT 0x%x\n",
26 MODULE_TAG, __func__, mmio_read_32(VCP_R_GIPC_IN_SET),
27 mmio_read_32(VCP_R_GIPC_IN_CLR),
28 mmio_read_32(VCP_GPR_CORE1_REBOOT));
29 return false;
30 }
31
32 mmio_write_32(VCP_R_CORE1_SW_RSTN_SET, BIT(0));
33
34 /* reset sec control */
35 mmio_write_32(VCP_R_SEC_CTRL_2, 0);
36
37 /* reset domain setting */
38 mmio_write_32(VCP_R_S_DOM_EN0_31, 0x0);
39 mmio_write_32(VCP_R_S_DOM_EN32_63, 0x0);
40 mmio_write_32(VCP_R_NS_DOM_EN0_31, 0x0);
41 mmio_write_32(VCP_R_NS_DOM_EN32_63, 0x0);
42
43 /* reset sec setting */
44 mmio_clrbits_32(VCP_R_DYN_SECURE,
45 RESET_NS_SECURE_B_REGION << VCP_NS_SECURE_B_REGION_ENABLE);
46
47 if (boot_ok)
48 mmio_write_32(VCP_GPR_CORE1_REBOOT, VCP_CORE_REBOOT_OK);
49
50 dsbsy();
51 return true;
52 }
53
mmup_smc_rstn_clr(void)54 bool mmup_smc_rstn_clr(void)
55 {
56 if ((mmio_read_32(VCP_R_CORE1_SW_RSTN_SET) & BIT(0)) == 1) {
57 ERROR("%s: [%s] mmup not reset set !\n", MODULE_TAG, __func__);
58 return false;
59 }
60
61 if ((get_mmup_fw_size() == 0) || get_mmup_l2tcm_offset() == 0) {
62 ERROR("%s: [%s] mmup no enough l2tcm to run !\n", MODULE_TAG, __func__);
63 return false;
64 }
65
66 mmio_write_32(VCP_R_SEC_DOMAIN_MMPC, VCP_DOMAIN_SET_MMPC);
67
68 /* enable IOVA Mode */
69 mmio_write_32(VCP_R_AXIOMMUEN_DEV_APC, BIT(0));
70
71 /* reset secure setting */
72 mmio_setbits_32(VCP_R_SEC_CTRL_2, CORE1_SEC_BIT_SEL);
73
74 /* l2tcm offset*/
75 mmio_setbits_32(VCP_R_SEC_CTRL, VCP_OFFSET_ENABLE_P | VCP_OFFSET_ENABLE_B);
76 mmio_write_32(R_L2TCM_OFFSET_RANGE_0_LOW, 0x0);
77 mmio_write_32(R_L2TCM_OFFSET_RANGE_0_HIGH, round_up(get_mmup_fw_size(), PAGE_SIZE));
78 mmio_write_32(R_L2TCM_OFFSET, get_mmup_l2tcm_offset());
79
80 /* start vcp-mmup */
81 mmio_write_32(VCP_R_CORE1_SW_RSTN_CLR, BIT(0));
82 dsbsy();
83 return true;
84 }
85