1*7ac6a76cSjason-ch chen /*
2*7ac6a76cSjason-ch chen * Copyright (c) 2022, MediaTek Inc. All rights reserved.
3*7ac6a76cSjason-ch chen *
4*7ac6a76cSjason-ch chen * SPDX-License-Identifier: BSD-3-Clause
5*7ac6a76cSjason-ch chen */
6*7ac6a76cSjason-ch chen
7*7ac6a76cSjason-ch chen #include <assert.h>
8*7ac6a76cSjason-ch chen #include <stddef.h>
9*7ac6a76cSjason-ch chen #include <common/debug.h>
10*7ac6a76cSjason-ch chen #include <drivers/delay_timer.h>
11*7ac6a76cSjason-ch chen #include <lib/mmio.h>
12*7ac6a76cSjason-ch chen #include <mt_spm.h>
13*7ac6a76cSjason-ch chen #include <mt_spm_internal.h>
14*7ac6a76cSjason-ch chen #include <mt_spm_reg.h>
15*7ac6a76cSjason-ch chen #include <mt_spm_resource_req.h>
16*7ac6a76cSjason-ch chen #include <plat_pm.h>
17*7ac6a76cSjason-ch chen #include <platform_def.h>
18*7ac6a76cSjason-ch chen
19*7ac6a76cSjason-ch chen /* Define and Declare */
20*7ac6a76cSjason-ch chen #define ROOT_CORE_ADDR_OFFSET (0x20000000)
21*7ac6a76cSjason-ch chen #define SPM_WAKEUP_EVENT_MASK_CLEAN_MASK (0xefffffff)
22*7ac6a76cSjason-ch chen #define SPM_INIT_DONE_US (20)
23*7ac6a76cSjason-ch chen
24*7ac6a76cSjason-ch chen static unsigned int mt_spm_bblpm_cnt;
25*7ac6a76cSjason-ch chen
26*7ac6a76cSjason-ch chen const char *wakeup_src_str[32] = {
27*7ac6a76cSjason-ch chen [0] = "R12_PCM_TIMER",
28*7ac6a76cSjason-ch chen [1] = "R12_RESERVED_DEBUG_B",
29*7ac6a76cSjason-ch chen [2] = "R12_KP_IRQ_B",
30*7ac6a76cSjason-ch chen [3] = "R12_APWDT_EVENT_B",
31*7ac6a76cSjason-ch chen [4] = "R12_APXGPT1_EVENT_B",
32*7ac6a76cSjason-ch chen [5] = "R12_CONN2AP_SPM_WAKEUP_B",
33*7ac6a76cSjason-ch chen [6] = "R12_EINT_EVENT_B",
34*7ac6a76cSjason-ch chen [7] = "R12_CONN_WDT_IRQ_B",
35*7ac6a76cSjason-ch chen [8] = "R12_CCIF0_EVENT_B",
36*7ac6a76cSjason-ch chen [9] = "R12_LOWBATTERY_IRQ_B",
37*7ac6a76cSjason-ch chen [10] = "R12_SC_SSPM2SPM_WAKEUP_B",
38*7ac6a76cSjason-ch chen [11] = "R12_SC_SCP2SPM_WAKEUP_B",
39*7ac6a76cSjason-ch chen [12] = "R12_SC_ADSP2SPM_WAKEUP_B",
40*7ac6a76cSjason-ch chen [13] = "R12_PCM_WDT_WAKEUP_B",
41*7ac6a76cSjason-ch chen [14] = "R12_USB_CDSC_B",
42*7ac6a76cSjason-ch chen [15] = "R12_USB_POWERDWN_B",
43*7ac6a76cSjason-ch chen [16] = "R12_SYS_TIMER_EVENT_B",
44*7ac6a76cSjason-ch chen [17] = "R12_EINT_EVENT_SECURE_B",
45*7ac6a76cSjason-ch chen [18] = "R12_CCIF1_EVENT_B",
46*7ac6a76cSjason-ch chen [19] = "R12_UART0_IRQ_B",
47*7ac6a76cSjason-ch chen [20] = "R12_AFE_IRQ_MCU_B",
48*7ac6a76cSjason-ch chen [21] = "R12_THERM_CTRL_EVENT_B",
49*7ac6a76cSjason-ch chen [22] = "R12_SYS_CIRQ_IRQ_B",
50*7ac6a76cSjason-ch chen [23] = "R12_MD2AP_PEER_EVENT_B",
51*7ac6a76cSjason-ch chen [24] = "R12_CSYSPWREQ_B",
52*7ac6a76cSjason-ch chen [25] = "R12_MD1_WDT_B",
53*7ac6a76cSjason-ch chen [26] = "R12_AP2AP_PEER_WAKEUPEVENT_B",
54*7ac6a76cSjason-ch chen [27] = "R12_SEJ_EVENT_B",
55*7ac6a76cSjason-ch chen [28] = "R12_SPM_CPU_WAKEUPEVENT_B",
56*7ac6a76cSjason-ch chen [29] = "R12_APUSYS",
57*7ac6a76cSjason-ch chen [30] = "R12_PCIE_BRIDGE_IRQ",
58*7ac6a76cSjason-ch chen [31] = "R12_PCIE_IRQ",
59*7ac6a76cSjason-ch chen };
60*7ac6a76cSjason-ch chen
61*7ac6a76cSjason-ch chen /* Function and API */
__spm_output_wake_reason(int state_id,const struct wake_status * wakesta)62*7ac6a76cSjason-ch chen wake_reason_t __spm_output_wake_reason(int state_id, const struct wake_status *wakesta)
63*7ac6a76cSjason-ch chen {
64*7ac6a76cSjason-ch chen uint32_t i, bk_vtcxo_dur, spm_26m_off_pct = 0U;
65*7ac6a76cSjason-ch chen wake_reason_t wr = WR_UNKNOWN;
66*7ac6a76cSjason-ch chen
67*7ac6a76cSjason-ch chen if (wakesta != NULL) {
68*7ac6a76cSjason-ch chen if (wakesta->abort != 0U) {
69*7ac6a76cSjason-ch chen ERROR("spmfw flow is aborted: 0x%x, timer_out = %u\n",
70*7ac6a76cSjason-ch chen wakesta->abort, wakesta->timer_out);
71*7ac6a76cSjason-ch chen } else {
72*7ac6a76cSjason-ch chen for (i = 0U; i < 32U; i++) {
73*7ac6a76cSjason-ch chen if ((wakesta->r12 & BIT(i)) != 0U) {
74*7ac6a76cSjason-ch chen INFO("wake up by %s, timer_out = %u\n",
75*7ac6a76cSjason-ch chen wakeup_src_str[i], wakesta->timer_out);
76*7ac6a76cSjason-ch chen wr = WR_WAKE_SRC;
77*7ac6a76cSjason-ch chen break;
78*7ac6a76cSjason-ch chen }
79*7ac6a76cSjason-ch chen }
80*7ac6a76cSjason-ch chen }
81*7ac6a76cSjason-ch chen
82*7ac6a76cSjason-ch chen INFO("r12 = 0x%x, r12_ext = 0x%x, r13 = 0x%x, debug_flag = 0x%x 0x%x\n",
83*7ac6a76cSjason-ch chen wakesta->r12, wakesta->r12_ext, wakesta->r13, wakesta->debug_flag,
84*7ac6a76cSjason-ch chen wakesta->debug_flag1);
85*7ac6a76cSjason-ch chen INFO("raw_sta = 0x%x 0x%x 0x%x, idle_sta = 0x%x, cg_check_sta = 0x%x\n",
86*7ac6a76cSjason-ch chen wakesta->raw_sta, wakesta->md32pcm_wakeup_sta,
87*7ac6a76cSjason-ch chen wakesta->md32pcm_event_sta, wakesta->idle_sta,
88*7ac6a76cSjason-ch chen wakesta->cg_check_sta);
89*7ac6a76cSjason-ch chen INFO("req_sta = 0x%x 0x%x 0x%x 0x%x 0x%x, isr = 0x%x\n",
90*7ac6a76cSjason-ch chen wakesta->req_sta0, wakesta->req_sta1, wakesta->req_sta2,
91*7ac6a76cSjason-ch chen wakesta->req_sta3, wakesta->req_sta4, wakesta->isr);
92*7ac6a76cSjason-ch chen INFO("rt_req_sta0 = 0x%x, rt_req_sta1 = 0x%x, rt_req_sta2 = 0x%x\n",
93*7ac6a76cSjason-ch chen wakesta->rt_req_sta0, wakesta->rt_req_sta1, wakesta->rt_req_sta2);
94*7ac6a76cSjason-ch chen INFO("rt_req_sta3 = 0x%x, dram_sw_con_3 = 0x%x, raw_ext_sta = 0x%x\n",
95*7ac6a76cSjason-ch chen wakesta->rt_req_sta3, wakesta->rt_req_sta4, wakesta->raw_ext_sta);
96*7ac6a76cSjason-ch chen INFO("wake_misc = 0x%x, pcm_flag = 0x%x 0x%x 0x%x 0x%x, req = 0x%x\n",
97*7ac6a76cSjason-ch chen wakesta->wake_misc, wakesta->sw_flag0, wakesta->sw_flag1,
98*7ac6a76cSjason-ch chen wakesta->b_sw_flag0, wakesta->b_sw_flag1, wakesta->src_req);
99*7ac6a76cSjason-ch chen INFO("clk_settle = 0x%x, wlk_cntcv_l = 0x%x, wlk_cntcv_h = 0x%x\n",
100*7ac6a76cSjason-ch chen wakesta->clk_settle, mmio_read_32(SYS_TIMER_VALUE_L),
101*7ac6a76cSjason-ch chen mmio_read_32(SYS_TIMER_VALUE_H));
102*7ac6a76cSjason-ch chen
103*7ac6a76cSjason-ch chen if (wakesta->timer_out != 0U) {
104*7ac6a76cSjason-ch chen bk_vtcxo_dur = mmio_read_32(SPM_BK_VTCXO_DUR);
105*7ac6a76cSjason-ch chen spm_26m_off_pct = (100 * bk_vtcxo_dur) / wakesta->timer_out;
106*7ac6a76cSjason-ch chen INFO("spm_26m_off_pct = %u\n", spm_26m_off_pct);
107*7ac6a76cSjason-ch chen }
108*7ac6a76cSjason-ch chen }
109*7ac6a76cSjason-ch chen
110*7ac6a76cSjason-ch chen return wr;
111*7ac6a76cSjason-ch chen }
112*7ac6a76cSjason-ch chen
__spm_set_cpu_status(unsigned int cpu)113*7ac6a76cSjason-ch chen void __spm_set_cpu_status(unsigned int cpu)
114*7ac6a76cSjason-ch chen {
115*7ac6a76cSjason-ch chen uint32_t root_core_addr;
116*7ac6a76cSjason-ch chen
117*7ac6a76cSjason-ch chen if (cpu < 8U) {
118*7ac6a76cSjason-ch chen mmio_write_32(ROOT_CPUTOP_ADDR, BIT(cpu));
119*7ac6a76cSjason-ch chen
120*7ac6a76cSjason-ch chen root_core_addr = SPM_CPU0_PWR_CON + (cpu * 0x4);
121*7ac6a76cSjason-ch chen root_core_addr += ROOT_CORE_ADDR_OFFSET;
122*7ac6a76cSjason-ch chen mmio_write_32(ROOT_CORE_ADDR, root_core_addr);
123*7ac6a76cSjason-ch chen
124*7ac6a76cSjason-ch chen /* Notify SSPM that preferred cpu wakeup */
125*7ac6a76cSjason-ch chen mmio_write_32(MCUPM_MBOX_WAKEUP_CPU, cpu);
126*7ac6a76cSjason-ch chen } else {
127*7ac6a76cSjason-ch chen ERROR("%s: error cpu number %d\n", __func__, cpu);
128*7ac6a76cSjason-ch chen }
129*7ac6a76cSjason-ch chen }
130*7ac6a76cSjason-ch chen
__spm_src_req_update(const struct pwr_ctrl * pwrctrl,unsigned int resource_usage)131*7ac6a76cSjason-ch chen void __spm_src_req_update(const struct pwr_ctrl *pwrctrl,
132*7ac6a76cSjason-ch chen unsigned int resource_usage)
133*7ac6a76cSjason-ch chen {
134*7ac6a76cSjason-ch chen uint8_t apsrc_req = ((resource_usage & MT_SPM_DRAM_S0) != 0U) ?
135*7ac6a76cSjason-ch chen 1 : pwrctrl->reg_spm_apsrc_req;
136*7ac6a76cSjason-ch chen uint8_t ddr_en_req = ((resource_usage & MT_SPM_DRAM_S1) != 0U) ?
137*7ac6a76cSjason-ch chen 1 : pwrctrl->reg_spm_ddren_req;
138*7ac6a76cSjason-ch chen uint8_t vrf18_req = ((resource_usage & MT_SPM_SYSPLL) != 0U) ?
139*7ac6a76cSjason-ch chen 1 : pwrctrl->reg_spm_vrf18_req;
140*7ac6a76cSjason-ch chen uint8_t infra_req = ((resource_usage & MT_SPM_INFRA) != 0U) ?
141*7ac6a76cSjason-ch chen 1 : pwrctrl->reg_spm_infra_req;
142*7ac6a76cSjason-ch chen uint8_t f26m_req = ((resource_usage & (MT_SPM_26M | MT_SPM_XO_FPM)) != 0U) ?
143*7ac6a76cSjason-ch chen 1 : pwrctrl->reg_spm_f26m_req;
144*7ac6a76cSjason-ch chen
145*7ac6a76cSjason-ch chen /*
146*7ac6a76cSjason-ch chen * if SPM_FLAG_SSPM_INFRA_SLEEP_MODE set,
147*7ac6a76cSjason-ch chen * clear sspm_srclkena_mask_b and sspm_infra_mask_b
148*7ac6a76cSjason-ch chen */
149*7ac6a76cSjason-ch chen uint8_t reg_sspm_srcclkena_mask_b =
150*7ac6a76cSjason-ch chen (pwrctrl->pcm_flags & SPM_FLAG_SSPM_INFRA_SLEEP_MODE)
151*7ac6a76cSjason-ch chen ? 0U : pwrctrl->reg_sspm_srcclkena_mask_b;
152*7ac6a76cSjason-ch chen
153*7ac6a76cSjason-ch chen uint8_t reg_sspm_infra_req_mask_b =
154*7ac6a76cSjason-ch chen (pwrctrl->pcm_flags & SPM_FLAG_SSPM_INFRA_SLEEP_MODE)
155*7ac6a76cSjason-ch chen ? 0 : pwrctrl->reg_sspm_infra_req_mask_b;
156*7ac6a76cSjason-ch chen
157*7ac6a76cSjason-ch chen /* SPM_SRC_REQ */
158*7ac6a76cSjason-ch chen mmio_write_32(SPM_SRC_REQ,
159*7ac6a76cSjason-ch chen ((apsrc_req & 0x1) << 0) |
160*7ac6a76cSjason-ch chen ((f26m_req & 0x1) << 1) |
161*7ac6a76cSjason-ch chen ((infra_req & 0x1) << 3) |
162*7ac6a76cSjason-ch chen ((vrf18_req & 0x1) << 4) |
163*7ac6a76cSjason-ch chen ((ddr_en_req & 0x1) << 7) |
164*7ac6a76cSjason-ch chen ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
165*7ac6a76cSjason-ch chen ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
166*7ac6a76cSjason-ch chen ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
167*7ac6a76cSjason-ch chen ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
168*7ac6a76cSjason-ch chen ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
169*7ac6a76cSjason-ch chen
170*7ac6a76cSjason-ch chen /* SPM_SRC_MASK */
171*7ac6a76cSjason-ch chen mmio_write_32(SPM_SRC_MASK,
172*7ac6a76cSjason-ch chen ((pwrctrl->reg_md_0_srcclkena_mask_b & 0x1) << 0) |
173*7ac6a76cSjason-ch chen ((pwrctrl->reg_md_0_infra_req_mask_b & 0x1) << 1) |
174*7ac6a76cSjason-ch chen ((pwrctrl->reg_md_0_apsrc_req_mask_b & 0x1) << 2) |
175*7ac6a76cSjason-ch chen ((pwrctrl->reg_md_0_vrf18_req_mask_b & 0x1) << 3) |
176*7ac6a76cSjason-ch chen ((pwrctrl->reg_md_0_ddren_req_mask_b & 0x1) << 4) |
177*7ac6a76cSjason-ch chen ((pwrctrl->reg_md_1_srcclkena_mask_b & 0x1) << 5) |
178*7ac6a76cSjason-ch chen ((pwrctrl->reg_md_1_infra_req_mask_b & 0x1) << 6) |
179*7ac6a76cSjason-ch chen ((pwrctrl->reg_md_1_apsrc_req_mask_b & 0x1) << 7) |
180*7ac6a76cSjason-ch chen ((pwrctrl->reg_md_1_vrf18_req_mask_b & 0x1) << 8) |
181*7ac6a76cSjason-ch chen ((pwrctrl->reg_md_1_ddren_req_mask_b & 0x1) << 9) |
182*7ac6a76cSjason-ch chen ((pwrctrl->reg_conn_srcclkena_mask_b & 0x1) << 10) |
183*7ac6a76cSjason-ch chen ((pwrctrl->reg_conn_srcclkenb_mask_b & 0x1) << 11) |
184*7ac6a76cSjason-ch chen ((pwrctrl->reg_conn_infra_req_mask_b & 0x1) << 12) |
185*7ac6a76cSjason-ch chen ((pwrctrl->reg_conn_apsrc_req_mask_b & 0x1) << 13) |
186*7ac6a76cSjason-ch chen ((pwrctrl->reg_conn_vrf18_req_mask_b & 0x1) << 14) |
187*7ac6a76cSjason-ch chen ((pwrctrl->reg_conn_ddren_req_mask_b & 0x1) << 15) |
188*7ac6a76cSjason-ch chen ((pwrctrl->reg_conn_vfe28_mask_b & 0x1) << 16) |
189*7ac6a76cSjason-ch chen ((pwrctrl->reg_srcclkeni_srcclkena_mask_b & 0x7) << 17) |
190*7ac6a76cSjason-ch chen ((pwrctrl->reg_srcclkeni_infra_req_mask_b & 0x7) << 20) |
191*7ac6a76cSjason-ch chen ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 25) |
192*7ac6a76cSjason-ch chen ((pwrctrl->reg_infrasys_ddren_req_mask_b & 0x1) << 26) |
193*7ac6a76cSjason-ch chen ((reg_sspm_srcclkena_mask_b & 0x1) << 27) |
194*7ac6a76cSjason-ch chen ((reg_sspm_infra_req_mask_b & 0x1) << 28) |
195*7ac6a76cSjason-ch chen ((pwrctrl->reg_sspm_apsrc_req_mask_b & 0x1) << 29) |
196*7ac6a76cSjason-ch chen ((pwrctrl->reg_sspm_vrf18_req_mask_b & 0x1) << 30) |
197*7ac6a76cSjason-ch chen ((pwrctrl->reg_sspm_ddren_req_mask_b & 0x1) << 31));
198*7ac6a76cSjason-ch chen }
199*7ac6a76cSjason-ch chen
__spm_set_power_control(const struct pwr_ctrl * pwrctrl)200*7ac6a76cSjason-ch chen void __spm_set_power_control(const struct pwr_ctrl *pwrctrl)
201*7ac6a76cSjason-ch chen {
202*7ac6a76cSjason-ch chen /* Auto-gen Start */
203*7ac6a76cSjason-ch chen
204*7ac6a76cSjason-ch chen /* SPM_AP_STANDBY_CON */
205*7ac6a76cSjason-ch chen mmio_write_32(SPM_AP_STANDBY_CON,
206*7ac6a76cSjason-ch chen ((pwrctrl->reg_wfi_op & 0x1) << 0) |
207*7ac6a76cSjason-ch chen ((pwrctrl->reg_wfi_type & 0x1) << 1) |
208*7ac6a76cSjason-ch chen ((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) |
209*7ac6a76cSjason-ch chen ((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) |
210*7ac6a76cSjason-ch chen ((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) |
211*7ac6a76cSjason-ch chen ((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) |
212*7ac6a76cSjason-ch chen ((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) |
213*7ac6a76cSjason-ch chen ((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29));
214*7ac6a76cSjason-ch chen
215*7ac6a76cSjason-ch chen /* SPM_SRC6_MASK */
216*7ac6a76cSjason-ch chen mmio_write_32(SPM_SRC6_MASK,
217*7ac6a76cSjason-ch chen ((pwrctrl->reg_ccif_event_infra_req_mask_b & 0xffff) << 0) |
218*7ac6a76cSjason-ch chen ((pwrctrl->reg_ccif_event_apsrc_req_mask_b & 0xffff) << 16));
219*7ac6a76cSjason-ch chen
220*7ac6a76cSjason-ch chen /* SPM_SRC_REQ */
221*7ac6a76cSjason-ch chen mmio_write_32(SPM_SRC_REQ,
222*7ac6a76cSjason-ch chen ((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) |
223*7ac6a76cSjason-ch chen ((pwrctrl->reg_spm_f26m_req & 0x1) << 1) |
224*7ac6a76cSjason-ch chen ((pwrctrl->reg_spm_infra_req & 0x1) << 3) |
225*7ac6a76cSjason-ch chen ((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) |
226*7ac6a76cSjason-ch chen ((pwrctrl->reg_spm_ddren_req & 0x1) << 7) |
227*7ac6a76cSjason-ch chen ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
228*7ac6a76cSjason-ch chen ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
229*7ac6a76cSjason-ch chen ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
230*7ac6a76cSjason-ch chen ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
231*7ac6a76cSjason-ch chen ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
232*7ac6a76cSjason-ch chen
233*7ac6a76cSjason-ch chen /* SPM_SRC_MASK */
234*7ac6a76cSjason-ch chen mmio_write_32(SPM_SRC_MASK,
235*7ac6a76cSjason-ch chen ((pwrctrl->reg_md_0_srcclkena_mask_b & 0x1) << 0) |
236*7ac6a76cSjason-ch chen ((pwrctrl->reg_md_0_infra_req_mask_b & 0x1) << 1) |
237*7ac6a76cSjason-ch chen ((pwrctrl->reg_md_0_apsrc_req_mask_b & 0x1) << 2) |
238*7ac6a76cSjason-ch chen ((pwrctrl->reg_md_0_vrf18_req_mask_b & 0x1) << 3) |
239*7ac6a76cSjason-ch chen ((pwrctrl->reg_md_0_ddren_req_mask_b & 0x1) << 4) |
240*7ac6a76cSjason-ch chen ((pwrctrl->reg_md_1_srcclkena_mask_b & 0x1) << 5) |
241*7ac6a76cSjason-ch chen ((pwrctrl->reg_md_1_infra_req_mask_b & 0x1) << 6) |
242*7ac6a76cSjason-ch chen ((pwrctrl->reg_md_1_apsrc_req_mask_b & 0x1) << 7) |
243*7ac6a76cSjason-ch chen ((pwrctrl->reg_md_1_vrf18_req_mask_b & 0x1) << 8) |
244*7ac6a76cSjason-ch chen ((pwrctrl->reg_md_1_ddren_req_mask_b & 0x1) << 9) |
245*7ac6a76cSjason-ch chen ((pwrctrl->reg_conn_srcclkena_mask_b & 0x1) << 10) |
246*7ac6a76cSjason-ch chen ((pwrctrl->reg_conn_srcclkenb_mask_b & 0x1) << 11) |
247*7ac6a76cSjason-ch chen ((pwrctrl->reg_conn_infra_req_mask_b & 0x1) << 12) |
248*7ac6a76cSjason-ch chen ((pwrctrl->reg_conn_apsrc_req_mask_b & 0x1) << 13) |
249*7ac6a76cSjason-ch chen ((pwrctrl->reg_conn_vrf18_req_mask_b & 0x1) << 14) |
250*7ac6a76cSjason-ch chen ((pwrctrl->reg_conn_ddren_req_mask_b & 0x1) << 15) |
251*7ac6a76cSjason-ch chen ((pwrctrl->reg_conn_vfe28_mask_b & 0x1) << 16) |
252*7ac6a76cSjason-ch chen ((pwrctrl->reg_srcclkeni_srcclkena_mask_b & 0x7) << 17) |
253*7ac6a76cSjason-ch chen ((pwrctrl->reg_srcclkeni_infra_req_mask_b & 0x7) << 20) |
254*7ac6a76cSjason-ch chen ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 25) |
255*7ac6a76cSjason-ch chen ((pwrctrl->reg_infrasys_ddren_req_mask_b & 0x1) << 26) |
256*7ac6a76cSjason-ch chen ((pwrctrl->reg_sspm_srcclkena_mask_b & 0x1) << 27) |
257*7ac6a76cSjason-ch chen ((pwrctrl->reg_sspm_infra_req_mask_b & 0x1) << 28) |
258*7ac6a76cSjason-ch chen ((pwrctrl->reg_sspm_apsrc_req_mask_b & 0x1) << 29) |
259*7ac6a76cSjason-ch chen ((pwrctrl->reg_sspm_vrf18_req_mask_b & 0x1) << 30) |
260*7ac6a76cSjason-ch chen ((pwrctrl->reg_sspm_ddren_req_mask_b & 0x1) << 31));
261*7ac6a76cSjason-ch chen
262*7ac6a76cSjason-ch chen /* SPM_SRC2_MASK */
263*7ac6a76cSjason-ch chen mmio_write_32(SPM_SRC2_MASK,
264*7ac6a76cSjason-ch chen ((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 0) |
265*7ac6a76cSjason-ch chen ((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 1) |
266*7ac6a76cSjason-ch chen ((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 2) |
267*7ac6a76cSjason-ch chen ((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 3) |
268*7ac6a76cSjason-ch chen ((pwrctrl->reg_scp_ddren_req_mask_b & 0x1) << 4) |
269*7ac6a76cSjason-ch chen ((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 5) |
270*7ac6a76cSjason-ch chen ((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 6) |
271*7ac6a76cSjason-ch chen ((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 7) |
272*7ac6a76cSjason-ch chen ((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 8) |
273*7ac6a76cSjason-ch chen ((pwrctrl->reg_audio_dsp_ddren_req_mask_b & 0x1) << 9) |
274*7ac6a76cSjason-ch chen ((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 10) |
275*7ac6a76cSjason-ch chen ((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 11) |
276*7ac6a76cSjason-ch chen ((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 12) |
277*7ac6a76cSjason-ch chen ((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 13) |
278*7ac6a76cSjason-ch chen ((pwrctrl->reg_ufs_ddren_req_mask_b & 0x1) << 14) |
279*7ac6a76cSjason-ch chen ((pwrctrl->reg_disp0_apsrc_req_mask_b & 0x1) << 15) |
280*7ac6a76cSjason-ch chen ((pwrctrl->reg_disp0_ddren_req_mask_b & 0x1) << 16) |
281*7ac6a76cSjason-ch chen ((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 17) |
282*7ac6a76cSjason-ch chen ((pwrctrl->reg_disp1_ddren_req_mask_b & 0x1) << 18) |
283*7ac6a76cSjason-ch chen ((pwrctrl->reg_gce_infra_req_mask_b & 0x1) << 19) |
284*7ac6a76cSjason-ch chen ((pwrctrl->reg_gce_apsrc_req_mask_b & 0x1) << 20) |
285*7ac6a76cSjason-ch chen ((pwrctrl->reg_gce_vrf18_req_mask_b & 0x1) << 21) |
286*7ac6a76cSjason-ch chen ((pwrctrl->reg_gce_ddren_req_mask_b & 0x1) << 22) |
287*7ac6a76cSjason-ch chen ((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 23) |
288*7ac6a76cSjason-ch chen ((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 24) |
289*7ac6a76cSjason-ch chen ((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 25) |
290*7ac6a76cSjason-ch chen ((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 26) |
291*7ac6a76cSjason-ch chen ((pwrctrl->reg_apu_ddren_req_mask_b & 0x1) << 27) |
292*7ac6a76cSjason-ch chen ((pwrctrl->reg_cg_check_srcclkena_mask_b & 0x1) << 28) |
293*7ac6a76cSjason-ch chen ((pwrctrl->reg_cg_check_apsrc_req_mask_b & 0x1) << 29) |
294*7ac6a76cSjason-ch chen ((pwrctrl->reg_cg_check_vrf18_req_mask_b & 0x1) << 30) |
295*7ac6a76cSjason-ch chen ((pwrctrl->reg_cg_check_ddren_req_mask_b & 0x1) << 31));
296*7ac6a76cSjason-ch chen
297*7ac6a76cSjason-ch chen /* SPM_SRC3_MASK */
298*7ac6a76cSjason-ch chen mmio_write_32(SPM_SRC3_MASK,
299*7ac6a76cSjason-ch chen ((pwrctrl->reg_dvfsrc_event_trigger_mask_b & 0x1) << 0) |
300*7ac6a76cSjason-ch chen ((pwrctrl->reg_sw2spm_wakeup_mask_b & 0xf) << 1) |
301*7ac6a76cSjason-ch chen ((pwrctrl->reg_adsp2spm_wakeup_mask_b & 0x1) << 5) |
302*7ac6a76cSjason-ch chen ((pwrctrl->reg_sspm2spm_wakeup_mask_b & 0xf) << 6) |
303*7ac6a76cSjason-ch chen ((pwrctrl->reg_scp2spm_wakeup_mask_b & 0x1) << 10) |
304*7ac6a76cSjason-ch chen ((pwrctrl->reg_csyspwrup_ack_mask & 0x1) << 11) |
305*7ac6a76cSjason-ch chen ((pwrctrl->reg_spm_reserved_srcclkena_mask_b & 0x1) << 12) |
306*7ac6a76cSjason-ch chen ((pwrctrl->reg_spm_reserved_infra_req_mask_b & 0x1) << 13) |
307*7ac6a76cSjason-ch chen ((pwrctrl->reg_spm_reserved_apsrc_req_mask_b & 0x1) << 14) |
308*7ac6a76cSjason-ch chen ((pwrctrl->reg_spm_reserved_vrf18_req_mask_b & 0x1) << 15) |
309*7ac6a76cSjason-ch chen ((pwrctrl->reg_spm_reserved_ddren_req_mask_b & 0x1) << 16) |
310*7ac6a76cSjason-ch chen ((pwrctrl->reg_mcupm_srcclkena_mask_b & 0x1) << 17) |
311*7ac6a76cSjason-ch chen ((pwrctrl->reg_mcupm_infra_req_mask_b & 0x1) << 18) |
312*7ac6a76cSjason-ch chen ((pwrctrl->reg_mcupm_apsrc_req_mask_b & 0x1) << 19) |
313*7ac6a76cSjason-ch chen ((pwrctrl->reg_mcupm_vrf18_req_mask_b & 0x1) << 20) |
314*7ac6a76cSjason-ch chen ((pwrctrl->reg_mcupm_ddren_req_mask_b & 0x1) << 21) |
315*7ac6a76cSjason-ch chen ((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 22) |
316*7ac6a76cSjason-ch chen ((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 23) |
317*7ac6a76cSjason-ch chen ((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 24) |
318*7ac6a76cSjason-ch chen ((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 25) |
319*7ac6a76cSjason-ch chen ((pwrctrl->reg_msdc0_ddren_req_mask_b & 0x1) << 26) |
320*7ac6a76cSjason-ch chen ((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 27) |
321*7ac6a76cSjason-ch chen ((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 28) |
322*7ac6a76cSjason-ch chen ((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 29) |
323*7ac6a76cSjason-ch chen ((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 30) |
324*7ac6a76cSjason-ch chen ((pwrctrl->reg_msdc1_ddren_req_mask_b & 0x1) << 31));
325*7ac6a76cSjason-ch chen
326*7ac6a76cSjason-ch chen /* SPM_SRC4_MASK */
327*7ac6a76cSjason-ch chen mmio_write_32(SPM_SRC4_MASK,
328*7ac6a76cSjason-ch chen ((pwrctrl->reg_ccif_event_srcclkena_mask_b & 0xffff) << 0) |
329*7ac6a76cSjason-ch chen ((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 16) |
330*7ac6a76cSjason-ch chen ((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 17) |
331*7ac6a76cSjason-ch chen ((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 18) |
332*7ac6a76cSjason-ch chen ((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 19) |
333*7ac6a76cSjason-ch chen ((pwrctrl->reg_bak_psri_ddren_req_mask_b & 0x1) << 20) |
334*7ac6a76cSjason-ch chen ((pwrctrl->reg_dramc_md32_infra_req_mask_b & 0x3) << 21) |
335*7ac6a76cSjason-ch chen ((pwrctrl->reg_dramc_md32_vrf18_req_mask_b & 0x3) << 23) |
336*7ac6a76cSjason-ch chen ((pwrctrl->reg_conn_srcclkenb2pwrap_mask_b & 0x1) << 25) |
337*7ac6a76cSjason-ch chen ((pwrctrl->reg_dramc_md32_apsrc_req_mask_b & 0x3) << 26));
338*7ac6a76cSjason-ch chen
339*7ac6a76cSjason-ch chen /* SPM_SRC5_MASK */
340*7ac6a76cSjason-ch chen mmio_write_32(SPM_SRC5_MASK,
341*7ac6a76cSjason-ch chen ((pwrctrl->reg_mcusys_merge_apsrc_req_mask_b & 0x1ff) << 0) |
342*7ac6a76cSjason-ch chen ((pwrctrl->reg_mcusys_merge_ddren_req_mask_b & 0x1ff) << 9) |
343*7ac6a76cSjason-ch chen ((pwrctrl->reg_afe_srcclkena_mask_b & 0x1) << 18) |
344*7ac6a76cSjason-ch chen ((pwrctrl->reg_afe_infra_req_mask_b & 0x1) << 19) |
345*7ac6a76cSjason-ch chen ((pwrctrl->reg_afe_apsrc_req_mask_b & 0x1) << 20) |
346*7ac6a76cSjason-ch chen ((pwrctrl->reg_afe_vrf18_req_mask_b & 0x1) << 21) |
347*7ac6a76cSjason-ch chen ((pwrctrl->reg_afe_ddren_req_mask_b & 0x1) << 22) |
348*7ac6a76cSjason-ch chen ((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 23) |
349*7ac6a76cSjason-ch chen ((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 24) |
350*7ac6a76cSjason-ch chen ((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 25) |
351*7ac6a76cSjason-ch chen ((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 26) |
352*7ac6a76cSjason-ch chen ((pwrctrl->reg_msdc2_ddren_req_mask_b & 0x1) << 27));
353*7ac6a76cSjason-ch chen
354*7ac6a76cSjason-ch chen /* SPM_WAKEUP_EVENT_MASK */
355*7ac6a76cSjason-ch chen mmio_write_32(SPM_WAKEUP_EVENT_MASK,
356*7ac6a76cSjason-ch chen ((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0));
357*7ac6a76cSjason-ch chen
358*7ac6a76cSjason-ch chen /* SPM_WAKEUP_EVENT_EXT_MASK */
359*7ac6a76cSjason-ch chen mmio_write_32(SPM_WAKEUP_EVENT_EXT_MASK,
360*7ac6a76cSjason-ch chen ((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0));
361*7ac6a76cSjason-ch chen
362*7ac6a76cSjason-ch chen /* SPM_SRC7_MASK */
363*7ac6a76cSjason-ch chen mmio_write_32(SPM_SRC7_MASK,
364*7ac6a76cSjason-ch chen ((pwrctrl->reg_pcie_srcclkena_mask_b & 0x1) << 0) |
365*7ac6a76cSjason-ch chen ((pwrctrl->reg_pcie_infra_req_mask_b & 0x1) << 1) |
366*7ac6a76cSjason-ch chen ((pwrctrl->reg_pcie_apsrc_req_mask_b & 0x1) << 2) |
367*7ac6a76cSjason-ch chen ((pwrctrl->reg_pcie_vrf18_req_mask_b & 0x1) << 3) |
368*7ac6a76cSjason-ch chen ((pwrctrl->reg_pcie_ddren_req_mask_b & 0x1) << 4) |
369*7ac6a76cSjason-ch chen ((pwrctrl->reg_dpmaif_srcclkena_mask_b & 0x1) << 5) |
370*7ac6a76cSjason-ch chen ((pwrctrl->reg_dpmaif_infra_req_mask_b & 0x1) << 6) |
371*7ac6a76cSjason-ch chen ((pwrctrl->reg_dpmaif_apsrc_req_mask_b & 0x1) << 7) |
372*7ac6a76cSjason-ch chen ((pwrctrl->reg_dpmaif_vrf18_req_mask_b & 0x1) << 8) |
373*7ac6a76cSjason-ch chen ((pwrctrl->reg_dpmaif_ddren_req_mask_b & 0x1) << 9));
374*7ac6a76cSjason-ch chen /* Auto-gen End */
375*7ac6a76cSjason-ch chen }
376*7ac6a76cSjason-ch chen
__spm_disable_pcm_timer(void)377*7ac6a76cSjason-ch chen void __spm_disable_pcm_timer(void)
378*7ac6a76cSjason-ch chen {
379*7ac6a76cSjason-ch chen mmio_clrsetbits_32(PCM_CON1, RG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY);
380*7ac6a76cSjason-ch chen }
381*7ac6a76cSjason-ch chen
382*7ac6a76cSjason-ch chen
__spm_set_wakeup_event(const struct pwr_ctrl * pwrctrl)383*7ac6a76cSjason-ch chen void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
384*7ac6a76cSjason-ch chen {
385*7ac6a76cSjason-ch chen uint32_t val, mask;
386*7ac6a76cSjason-ch chen
387*7ac6a76cSjason-ch chen /* toggle event counter clear */
388*7ac6a76cSjason-ch chen mmio_setbits_32(PCM_CON1,
389*7ac6a76cSjason-ch chen SPM_REGWR_CFG_KEY | REG_SPM_EVENT_COUNTER_CLR_LSB);
390*7ac6a76cSjason-ch chen
391*7ac6a76cSjason-ch chen /* toggle for reset SYS TIMER start point */
392*7ac6a76cSjason-ch chen mmio_setbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB);
393*7ac6a76cSjason-ch chen
394*7ac6a76cSjason-ch chen if (pwrctrl->timer_val_cust == 0U) {
395*7ac6a76cSjason-ch chen val = pwrctrl->timer_val ? (pwrctrl->timer_val) : (PCM_TIMER_MAX);
396*7ac6a76cSjason-ch chen } else {
397*7ac6a76cSjason-ch chen val = pwrctrl->timer_val_cust;
398*7ac6a76cSjason-ch chen }
399*7ac6a76cSjason-ch chen
400*7ac6a76cSjason-ch chen mmio_write_32(PCM_TIMER_VAL, val);
401*7ac6a76cSjason-ch chen mmio_setbits_32(PCM_CON1, (SPM_REGWR_CFG_KEY | RG_PCM_TIMER_EN_LSB));
402*7ac6a76cSjason-ch chen
403*7ac6a76cSjason-ch chen /* unmask AP wakeup source */
404*7ac6a76cSjason-ch chen if (pwrctrl->wake_src_cust == 0U) {
405*7ac6a76cSjason-ch chen mask = pwrctrl->wake_src;
406*7ac6a76cSjason-ch chen } else {
407*7ac6a76cSjason-ch chen mask = pwrctrl->wake_src_cust;
408*7ac6a76cSjason-ch chen }
409*7ac6a76cSjason-ch chen
410*7ac6a76cSjason-ch chen if (pwrctrl->reg_csyspwrup_ack_mask != 0U) {
411*7ac6a76cSjason-ch chen mask &= ~R12_CSYSPWREQ_B;
412*7ac6a76cSjason-ch chen }
413*7ac6a76cSjason-ch chen
414*7ac6a76cSjason-ch chen mmio_write_32(SPM_WAKEUP_EVENT_MASK, ~mask);
415*7ac6a76cSjason-ch chen
416*7ac6a76cSjason-ch chen /* unmask SPM ISR (keep TWAM setting) */
417*7ac6a76cSjason-ch chen mmio_setbits_32(SPM_IRQ_MASK, ISRM_RET_IRQ_AUX);
418*7ac6a76cSjason-ch chen
419*7ac6a76cSjason-ch chen /* toggle event counter clear */
420*7ac6a76cSjason-ch chen mmio_clrsetbits_32(PCM_CON1, REG_SPM_EVENT_COUNTER_CLR_LSB,
421*7ac6a76cSjason-ch chen SPM_REGWR_CFG_KEY);
422*7ac6a76cSjason-ch chen /* toggle for reset SYS TIMER start point */
423*7ac6a76cSjason-ch chen mmio_clrbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB);
424*7ac6a76cSjason-ch chen }
425*7ac6a76cSjason-ch chen
__spm_set_pcm_flags(struct pwr_ctrl * pwrctrl)426*7ac6a76cSjason-ch chen void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl)
427*7ac6a76cSjason-ch chen {
428*7ac6a76cSjason-ch chen /* set PCM flags and data */
429*7ac6a76cSjason-ch chen if (pwrctrl->pcm_flags_cust_clr != 0U) {
430*7ac6a76cSjason-ch chen pwrctrl->pcm_flags &= ~pwrctrl->pcm_flags_cust_clr;
431*7ac6a76cSjason-ch chen }
432*7ac6a76cSjason-ch chen
433*7ac6a76cSjason-ch chen if (pwrctrl->pcm_flags_cust_set != 0U) {
434*7ac6a76cSjason-ch chen pwrctrl->pcm_flags |= pwrctrl->pcm_flags_cust_set;
435*7ac6a76cSjason-ch chen }
436*7ac6a76cSjason-ch chen
437*7ac6a76cSjason-ch chen if (pwrctrl->pcm_flags1_cust_clr != 0U) {
438*7ac6a76cSjason-ch chen pwrctrl->pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr;
439*7ac6a76cSjason-ch chen }
440*7ac6a76cSjason-ch chen
441*7ac6a76cSjason-ch chen if (pwrctrl->pcm_flags1_cust_set != 0U) {
442*7ac6a76cSjason-ch chen pwrctrl->pcm_flags1 |= pwrctrl->pcm_flags1_cust_set;
443*7ac6a76cSjason-ch chen }
444*7ac6a76cSjason-ch chen
445*7ac6a76cSjason-ch chen mmio_write_32(SPM_SW_FLAG_0, pwrctrl->pcm_flags);
446*7ac6a76cSjason-ch chen
447*7ac6a76cSjason-ch chen mmio_write_32(SPM_SW_FLAG_1, pwrctrl->pcm_flags1);
448*7ac6a76cSjason-ch chen
449*7ac6a76cSjason-ch chen mmio_write_32(SPM_SW_RSV_7, pwrctrl->pcm_flags);
450*7ac6a76cSjason-ch chen
451*7ac6a76cSjason-ch chen mmio_write_32(SPM_SW_RSV_8, pwrctrl->pcm_flags1);
452*7ac6a76cSjason-ch chen }
453*7ac6a76cSjason-ch chen
__spm_get_wakeup_status(struct wake_status * wakesta,unsigned int ext_status)454*7ac6a76cSjason-ch chen void __spm_get_wakeup_status(struct wake_status *wakesta,
455*7ac6a76cSjason-ch chen unsigned int ext_status)
456*7ac6a76cSjason-ch chen {
457*7ac6a76cSjason-ch chen wakesta->tr.comm.r12 = mmio_read_32(SPM_BK_WAKE_EVENT);
458*7ac6a76cSjason-ch chen wakesta->tr.comm.timer_out = mmio_read_32(SPM_BK_PCM_TIMER);
459*7ac6a76cSjason-ch chen wakesta->tr.comm.r13 = mmio_read_32(PCM_REG13_DATA);
460*7ac6a76cSjason-ch chen wakesta->tr.comm.req_sta0 = mmio_read_32(SRC_REQ_STA_0);
461*7ac6a76cSjason-ch chen wakesta->tr.comm.req_sta1 = mmio_read_32(SRC_REQ_STA_1);
462*7ac6a76cSjason-ch chen wakesta->tr.comm.req_sta2 = mmio_read_32(SRC_REQ_STA_2);
463*7ac6a76cSjason-ch chen wakesta->tr.comm.req_sta3 = mmio_read_32(SRC_REQ_STA_3);
464*7ac6a76cSjason-ch chen wakesta->tr.comm.req_sta4 = mmio_read_32(SRC_REQ_STA_4);
465*7ac6a76cSjason-ch chen
466*7ac6a76cSjason-ch chen wakesta->tr.comm.debug_flag = mmio_read_32(PCM_WDT_LATCH_SPARE_0);
467*7ac6a76cSjason-ch chen wakesta->tr.comm.debug_flag1 = mmio_read_32(PCM_WDT_LATCH_SPARE_1);
468*7ac6a76cSjason-ch chen
469*7ac6a76cSjason-ch chen if ((ext_status & SPM_INTERNAL_STATUS_HW_S1) != 0U) {
470*7ac6a76cSjason-ch chen wakesta->tr.comm.debug_flag |= (SPM_DBG_DEBUG_IDX_DDREN_WAKE |
471*7ac6a76cSjason-ch chen SPM_DBG_DEBUG_IDX_DDREN_SLEEP);
472*7ac6a76cSjason-ch chen mmio_write_32(PCM_WDT_LATCH_SPARE_0, wakesta->tr.comm.debug_flag);
473*7ac6a76cSjason-ch chen }
474*7ac6a76cSjason-ch chen
475*7ac6a76cSjason-ch chen wakesta->tr.comm.b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7);
476*7ac6a76cSjason-ch chen wakesta->tr.comm.b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8);
477*7ac6a76cSjason-ch chen
478*7ac6a76cSjason-ch chen /* record below spm info for debug */
479*7ac6a76cSjason-ch chen wakesta->r12 = mmio_read_32(SPM_BK_WAKE_EVENT);
480*7ac6a76cSjason-ch chen wakesta->r12_ext = mmio_read_32(SPM_WAKEUP_STA);
481*7ac6a76cSjason-ch chen wakesta->raw_sta = mmio_read_32(SPM_WAKEUP_STA);
482*7ac6a76cSjason-ch chen wakesta->raw_ext_sta = mmio_read_32(SPM_WAKEUP_EXT_STA);
483*7ac6a76cSjason-ch chen wakesta->md32pcm_wakeup_sta = mmio_read_32(MD32PCM_WAKEUP_STA);
484*7ac6a76cSjason-ch chen wakesta->md32pcm_event_sta = mmio_read_32(MD32PCM_EVENT_STA);
485*7ac6a76cSjason-ch chen wakesta->src_req = mmio_read_32(SPM_SRC_REQ);
486*7ac6a76cSjason-ch chen
487*7ac6a76cSjason-ch chen /* backup of SPM_WAKEUP_MISC */
488*7ac6a76cSjason-ch chen wakesta->wake_misc = mmio_read_32(SPM_BK_WAKE_MISC);
489*7ac6a76cSjason-ch chen
490*7ac6a76cSjason-ch chen /* get sleep time, backup of PCM_TIMER_OUT */
491*7ac6a76cSjason-ch chen wakesta->timer_out = mmio_read_32(SPM_BK_PCM_TIMER);
492*7ac6a76cSjason-ch chen
493*7ac6a76cSjason-ch chen /* get other SYS and co-clock status */
494*7ac6a76cSjason-ch chen wakesta->r13 = mmio_read_32(PCM_REG13_DATA);
495*7ac6a76cSjason-ch chen wakesta->idle_sta = mmio_read_32(SUBSYS_IDLE_STA);
496*7ac6a76cSjason-ch chen wakesta->req_sta0 = mmio_read_32(SRC_REQ_STA_0);
497*7ac6a76cSjason-ch chen wakesta->req_sta1 = mmio_read_32(SRC_REQ_STA_1);
498*7ac6a76cSjason-ch chen wakesta->req_sta2 = mmio_read_32(SRC_REQ_STA_2);
499*7ac6a76cSjason-ch chen wakesta->req_sta3 = mmio_read_32(SRC_REQ_STA_3);
500*7ac6a76cSjason-ch chen wakesta->req_sta4 = mmio_read_32(SRC_REQ_STA_4);
501*7ac6a76cSjason-ch chen
502*7ac6a76cSjason-ch chen /* get HW CG check status */
503*7ac6a76cSjason-ch chen wakesta->cg_check_sta = mmio_read_32(SPM_CG_CHECK_STA);
504*7ac6a76cSjason-ch chen
505*7ac6a76cSjason-ch chen /* get debug flag for PCM execution check */
506*7ac6a76cSjason-ch chen wakesta->debug_flag = mmio_read_32(PCM_WDT_LATCH_SPARE_0);
507*7ac6a76cSjason-ch chen wakesta->debug_flag1 = mmio_read_32(PCM_WDT_LATCH_SPARE_1);
508*7ac6a76cSjason-ch chen
509*7ac6a76cSjason-ch chen /* get backup SW flag status */
510*7ac6a76cSjason-ch chen wakesta->b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7);
511*7ac6a76cSjason-ch chen wakesta->b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8);
512*7ac6a76cSjason-ch chen
513*7ac6a76cSjason-ch chen wakesta->rt_req_sta0 = mmio_read_32(SPM_SW_RSV_2);
514*7ac6a76cSjason-ch chen wakesta->rt_req_sta1 = mmio_read_32(SPM_SW_RSV_3);
515*7ac6a76cSjason-ch chen wakesta->rt_req_sta2 = mmio_read_32(SPM_SW_RSV_4);
516*7ac6a76cSjason-ch chen wakesta->rt_req_sta3 = mmio_read_32(SPM_SW_RSV_5);
517*7ac6a76cSjason-ch chen wakesta->rt_req_sta4 = mmio_read_32(SPM_SW_RSV_6);
518*7ac6a76cSjason-ch chen
519*7ac6a76cSjason-ch chen /* get ISR status */
520*7ac6a76cSjason-ch chen wakesta->isr = mmio_read_32(SPM_IRQ_STA);
521*7ac6a76cSjason-ch chen
522*7ac6a76cSjason-ch chen /* get SW flag status */
523*7ac6a76cSjason-ch chen wakesta->sw_flag0 = mmio_read_32(SPM_SW_FLAG_0);
524*7ac6a76cSjason-ch chen wakesta->sw_flag1 = mmio_read_32(SPM_SW_FLAG_1);
525*7ac6a76cSjason-ch chen
526*7ac6a76cSjason-ch chen /* get CLK SETTLE */
527*7ac6a76cSjason-ch chen wakesta->clk_settle = mmio_read_32(SPM_CLK_SETTLE);
528*7ac6a76cSjason-ch chen
529*7ac6a76cSjason-ch chen /* check abort */
530*7ac6a76cSjason-ch chen wakesta->abort = ((wakesta->debug_flag & DEBUG_ABORT_MASK) |
531*7ac6a76cSjason-ch chen (wakesta->debug_flag1 & DEBUG_ABORT_MASK_1));
532*7ac6a76cSjason-ch chen }
533*7ac6a76cSjason-ch chen
__spm_clean_after_wakeup(void)534*7ac6a76cSjason-ch chen void __spm_clean_after_wakeup(void)
535*7ac6a76cSjason-ch chen {
536*7ac6a76cSjason-ch chen mmio_write_32(SPM_BK_WAKE_EVENT,
537*7ac6a76cSjason-ch chen (mmio_read_32(SPM_WAKEUP_STA) |
538*7ac6a76cSjason-ch chen mmio_read_32(SPM_BK_WAKE_EVENT)));
539*7ac6a76cSjason-ch chen mmio_write_32(SPM_CPU_WAKEUP_EVENT, 0U);
540*7ac6a76cSjason-ch chen
541*7ac6a76cSjason-ch chen /*
542*7ac6a76cSjason-ch chen * clean wakeup event raw status (for edge trigger event)
543*7ac6a76cSjason-ch chen * bit[28] for cpu wake up event
544*7ac6a76cSjason-ch chen */
545*7ac6a76cSjason-ch chen mmio_write_32(SPM_WAKEUP_EVENT_MASK, SPM_WAKEUP_EVENT_MASK_CLEAN_MASK);
546*7ac6a76cSjason-ch chen
547*7ac6a76cSjason-ch chen /* clean ISR status (except TWAM) */
548*7ac6a76cSjason-ch chen mmio_setbits_32(SPM_IRQ_MASK, ISRM_ALL_EXC_TWAM);
549*7ac6a76cSjason-ch chen mmio_write_32(SPM_IRQ_STA, ISRC_ALL_EXC_TWAM);
550*7ac6a76cSjason-ch chen mmio_write_32(SPM_SWINT_CLR, PCM_SW_INT_ALL);
551*7ac6a76cSjason-ch chen }
552*7ac6a76cSjason-ch chen
__spm_set_pcm_wdt(int en)553*7ac6a76cSjason-ch chen void __spm_set_pcm_wdt(int en)
554*7ac6a76cSjason-ch chen {
555*7ac6a76cSjason-ch chen mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_EN_LSB,
556*7ac6a76cSjason-ch chen SPM_REGWR_CFG_KEY);
557*7ac6a76cSjason-ch chen
558*7ac6a76cSjason-ch chen if (en == 1) {
559*7ac6a76cSjason-ch chen mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_WAKE_LSB,
560*7ac6a76cSjason-ch chen SPM_REGWR_CFG_KEY);
561*7ac6a76cSjason-ch chen
562*7ac6a76cSjason-ch chen if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX) {
563*7ac6a76cSjason-ch chen mmio_write_32(PCM_TIMER_VAL, PCM_TIMER_MAX);
564*7ac6a76cSjason-ch chen }
565*7ac6a76cSjason-ch chen
566*7ac6a76cSjason-ch chen mmio_write_32(PCM_WDT_VAL,
567*7ac6a76cSjason-ch chen mmio_read_32(PCM_TIMER_VAL) + PCM_WDT_TIMEOUT);
568*7ac6a76cSjason-ch chen mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | RG_PCM_WDT_EN_LSB);
569*7ac6a76cSjason-ch chen }
570*7ac6a76cSjason-ch chen }
571*7ac6a76cSjason-ch chen
__spm_send_cpu_wakeup_event(void)572*7ac6a76cSjason-ch chen void __spm_send_cpu_wakeup_event(void)
573*7ac6a76cSjason-ch chen {
574*7ac6a76cSjason-ch chen /* SPM will clear SPM_CPU_WAKEUP_EVENT */
575*7ac6a76cSjason-ch chen mmio_write_32(SPM_CPU_WAKEUP_EVENT, 1);
576*7ac6a76cSjason-ch chen }
577*7ac6a76cSjason-ch chen
__spm_ext_int_wakeup_req_clr(void)578*7ac6a76cSjason-ch chen void __spm_ext_int_wakeup_req_clr(void)
579*7ac6a76cSjason-ch chen {
580*7ac6a76cSjason-ch chen unsigned int reg = mmio_read_32(SPM_MD32_IRQ) & (~(0x1U << 0));
581*7ac6a76cSjason-ch chen
582*7ac6a76cSjason-ch chen mmio_write_32(EXT_INT_WAKEUP_REQ_CLR, mmio_read_32(ROOT_CPUTOP_ADDR));
583*7ac6a76cSjason-ch chen
584*7ac6a76cSjason-ch chen /* Clear spm2mcupm wakeup interrupt status */
585*7ac6a76cSjason-ch chen mmio_write_32(SPM_MD32_IRQ, reg);
586*7ac6a76cSjason-ch chen }
587*7ac6a76cSjason-ch chen
__spm_xo_soc_bblpm(int en)588*7ac6a76cSjason-ch chen void __spm_xo_soc_bblpm(int en)
589*7ac6a76cSjason-ch chen {
590*7ac6a76cSjason-ch chen if (en == 1) {
591*7ac6a76cSjason-ch chen mmio_clrsetbits_32(RC_M00_SRCLKEN_CFG,
592*7ac6a76cSjason-ch chen RC_SW_SRCCLKEN_FPM, RC_SW_SRCCLKEN_RC);
593*7ac6a76cSjason-ch chen assert(mt_spm_bblpm_cnt == 0);
594*7ac6a76cSjason-ch chen mt_spm_bblpm_cnt += 1;
595*7ac6a76cSjason-ch chen } else {
596*7ac6a76cSjason-ch chen mmio_clrsetbits_32(RC_M00_SRCLKEN_CFG,
597*7ac6a76cSjason-ch chen RC_SW_SRCCLKEN_RC, RC_SW_SRCCLKEN_FPM);
598*7ac6a76cSjason-ch chen mt_spm_bblpm_cnt -= 1;
599*7ac6a76cSjason-ch chen }
600*7ac6a76cSjason-ch chen }
601*7ac6a76cSjason-ch chen
__spm_hw_s1_state_monitor(int en,unsigned int * status)602*7ac6a76cSjason-ch chen void __spm_hw_s1_state_monitor(int en, unsigned int *status)
603*7ac6a76cSjason-ch chen {
604*7ac6a76cSjason-ch chen unsigned int reg = mmio_read_32(SPM_ACK_CHK_CON_3);
605*7ac6a76cSjason-ch chen
606*7ac6a76cSjason-ch chen if (en == 1) {
607*7ac6a76cSjason-ch chen reg = mmio_read_32(SPM_ACK_CHK_CON_3);
608*7ac6a76cSjason-ch chen reg &= ~SPM_ACK_CHK_3_CON_CLR_ALL;
609*7ac6a76cSjason-ch chen mmio_write_32(SPM_ACK_CHK_CON_3, reg);
610*7ac6a76cSjason-ch chen reg |= SPM_ACK_CHK_3_CON_EN;
611*7ac6a76cSjason-ch chen mmio_write_32(SPM_ACK_CHK_CON_3, reg);
612*7ac6a76cSjason-ch chen } else {
613*7ac6a76cSjason-ch chen if (((reg & SPM_ACK_CHK_3_CON_RESULT) != 0U) &&
614*7ac6a76cSjason-ch chen (status != NULL)) {
615*7ac6a76cSjason-ch chen *status |= SPM_INTERNAL_STATUS_HW_S1;
616*7ac6a76cSjason-ch chen }
617*7ac6a76cSjason-ch chen
618*7ac6a76cSjason-ch chen mmio_clrsetbits_32(SPM_ACK_CHK_CON_3, SPM_ACK_CHK_3_CON_EN,
619*7ac6a76cSjason-ch chen SPM_ACK_CHK_3_CON_HW_MODE_TRIG |
620*7ac6a76cSjason-ch chen SPM_ACK_CHK_3_CON_CLR_ALL);
621*7ac6a76cSjason-ch chen }
622*7ac6a76cSjason-ch chen }
623*7ac6a76cSjason-ch chen
624