188906b44SFlora Fu /*
288906b44SFlora Fu * Copyright (c) 2021, MediaTek Inc. All rights reserved.
388906b44SFlora Fu *
488906b44SFlora Fu * SPDX-License-Identifier: BSD-3-Clause
588906b44SFlora Fu */
688906b44SFlora Fu
788906b44SFlora Fu #include <common/debug.h>
888906b44SFlora Fu #include <drivers/console.h>
988906b44SFlora Fu #include <lib/mmio.h>
1088906b44SFlora Fu
11*296b5902SFlora Fu #include <apupwr_clkctl.h>
1288906b44SFlora Fu #include <mtk_apusys.h>
1388906b44SFlora Fu #include <plat/common/platform.h>
1488906b44SFlora Fu
apusys_kernel_ctrl(uint64_t x1,uint64_t x2,uint64_t x3,uint64_t x4,uint32_t * ret1)1588906b44SFlora Fu int32_t apusys_kernel_ctrl(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4,
1688906b44SFlora Fu uint32_t *ret1)
1788906b44SFlora Fu {
1888906b44SFlora Fu int32_t ret = 0L;
1988906b44SFlora Fu uint32_t request_ops;
2088906b44SFlora Fu
2188906b44SFlora Fu request_ops = (uint32_t)x1;
2288906b44SFlora Fu
2388906b44SFlora Fu switch (request_ops) {
2488906b44SFlora Fu case MTK_SIP_APU_START_MCU:
2588906b44SFlora Fu /* setup addr[33:32] in reviser */
2688906b44SFlora Fu mmio_write_32(REVISER_SECUREFW_CTXT, 0U);
2788906b44SFlora Fu mmio_write_32(REVISER_USDRFW_CTXT, 0U);
2888906b44SFlora Fu
2988906b44SFlora Fu /* setup secure sideband */
3088906b44SFlora Fu mmio_write_32(AO_SEC_FW,
3188906b44SFlora Fu (SEC_FW_NON_SECURE << SEC_FW_SHIFT_NS) |
3288906b44SFlora Fu (0U << SEC_FW_DOMAIN_SHIFT));
3388906b44SFlora Fu
3488906b44SFlora Fu /* setup boot address */
3588906b44SFlora Fu mmio_write_32(AO_MD32_BOOT_CTRL, 0U);
3688906b44SFlora Fu
3788906b44SFlora Fu /* setup pre-define region */
3888906b44SFlora Fu mmio_write_32(AO_MD32_PRE_DEFINE,
3988906b44SFlora Fu (PRE_DEFINE_CACHE_TCM << PRE_DEFINE_SHIFT_0G) |
4088906b44SFlora Fu (PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_1G) |
4188906b44SFlora Fu (PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_2G) |
4288906b44SFlora Fu (PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_3G));
4388906b44SFlora Fu
4488906b44SFlora Fu /* release runstall */
4588906b44SFlora Fu mmio_write_32(AO_MD32_SYS_CTRL, SYS_CTRL_RUN);
4688906b44SFlora Fu
4788906b44SFlora Fu INFO("[APUSYS] rev(0x%08x,0x%08x)\n",
4888906b44SFlora Fu mmio_read_32(REVISER_SECUREFW_CTXT),
4988906b44SFlora Fu mmio_read_32(REVISER_USDRFW_CTXT));
5088906b44SFlora Fu INFO("[APUSYS] ao(0x%08x,0x%08x,0x%08x,0x%08x,0x%08x)\n",
5188906b44SFlora Fu mmio_read_32(AO_SEC_FW),
5288906b44SFlora Fu mmio_read_32(AO_SEC_USR_FW),
5388906b44SFlora Fu mmio_read_32(AO_MD32_BOOT_CTRL),
5488906b44SFlora Fu mmio_read_32(AO_MD32_PRE_DEFINE),
5588906b44SFlora Fu mmio_read_32(AO_MD32_SYS_CTRL));
5688906b44SFlora Fu break;
5788906b44SFlora Fu case MTK_SIP_APU_STOP_MCU:
5888906b44SFlora Fu /* hold runstall */
5988906b44SFlora Fu mmio_write_32(AO_MD32_SYS_CTRL, SYS_CTRL_STALL);
6088906b44SFlora Fu
6188906b44SFlora Fu INFO("[APUSYS] md32_boot_ctrl=0x%08x,runstall=0x%08x\n",
6288906b44SFlora Fu mmio_read_32(AO_MD32_BOOT_CTRL),
6388906b44SFlora Fu mmio_read_32(AO_MD32_SYS_CTRL));
6488906b44SFlora Fu break;
65*296b5902SFlora Fu case MTK_SIP_APUPWR_BUS_PROT_CG_ON:
66*296b5902SFlora Fu apupwr_smc_bus_prot_cg_on();
67*296b5902SFlora Fu break;
68*296b5902SFlora Fu case MTK_SIP_APUPWR_BULK_PLL:
69*296b5902SFlora Fu ret = apupwr_smc_bulk_pll((bool)x2);
70*296b5902SFlora Fu break;
71*296b5902SFlora Fu case MTK_SIP_APUPWR_ACC_INIT_ALL:
72*296b5902SFlora Fu ret = apupwr_smc_acc_init_all();
73*296b5902SFlora Fu break;
74*296b5902SFlora Fu case MTK_SIP_APUPWR_ACC_TOP:
75*296b5902SFlora Fu apupwr_smc_acc_top((bool)x2);
76*296b5902SFlora Fu break;
7788906b44SFlora Fu default:
7888906b44SFlora Fu ERROR("%s, unknown request_ops=0x%x\n", __func__, request_ops);
7988906b44SFlora Fu break;
8088906b44SFlora Fu }
8188906b44SFlora Fu
8288906b44SFlora Fu return ret;
8388906b44SFlora Fu }
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