Home
last modified time | relevance | path

Searched refs:ctl (Results 1 – 18 of 18) sorted by relevance

/rk3399_ARM-atf/drivers/st/ddr/
H A Dstm32mp_ddr.c25 return (uintptr_t)priv->ctl; in get_base_addr()
49 stm32mp_ddr_start_sw_done(priv->ctl); in stm32mp_ddr_set_reg()
57 stm32mp_ddr_wait_sw_done_ack(priv->ctl); in stm32mp_ddr_set_reg()
65 void stm32mp_ddr_start_sw_done(struct stm32mp_ddrctl *ctl) in stm32mp_ddr_start_sw_done() argument
67 mmio_clrbits_32((uintptr_t)&ctl->swctl, DDRCTRL_SWCTL_SW_DONE); in stm32mp_ddr_start_sw_done()
69 (uintptr_t)&ctl->swctl, mmio_read_32((uintptr_t)&ctl->swctl)); in stm32mp_ddr_start_sw_done()
73 void stm32mp_ddr_wait_sw_done_ack(struct stm32mp_ddrctl *ctl) in stm32mp_ddr_wait_sw_done_ack() argument
78 mmio_setbits_32((uintptr_t)&ctl->swctl, DDRCTRL_SWCTL_SW_DONE); in stm32mp_ddr_wait_sw_done_ack()
80 (uintptr_t)&ctl->swctl, mmio_read_32((uintptr_t)&ctl->swctl)); in stm32mp_ddr_wait_sw_done_ack()
84 swstat = mmio_read_32((uintptr_t)&ctl->swstat); in stm32mp_ddr_wait_sw_done_ack()
[all …]
H A Dstm32mp1_ddr.c285 stat = mmio_read_32((uintptr_t)&priv->ctl->stat); in stm32mp1_wait_operating_mode()
289 (uintptr_t)&priv->ctl->stat, stat); in stm32mp1_wait_operating_mode()
319 (uintptr_t)&priv->ctl->stat, stat); in stm32mp1_wait_operating_mode()
336 while ((mmio_read_32((uintptr_t)&priv->ctl->mrstat) & in stm32mp1_mode_register_write()
349 mmio_write_32((uintptr_t)&priv->ctl->mrctrl0, mrctrl0); in stm32mp1_mode_register_write()
351 (uintptr_t)&priv->ctl->mrctrl0, in stm32mp1_mode_register_write()
352 mmio_read_32((uintptr_t)&priv->ctl->mrctrl0), mrctrl0); in stm32mp1_mode_register_write()
353 mmio_write_32((uintptr_t)&priv->ctl->mrctrl1, data); in stm32mp1_mode_register_write()
355 (uintptr_t)&priv->ctl->mrctrl1, in stm32mp1_mode_register_write()
356 mmio_read_32((uintptr_t)&priv->ctl->mrctrl1)); in stm32mp1_mode_register_write()
[all …]
H A Dstm32mp2_ddr_helpers.c33 static void set_qd1_qd3_update_conditions(struct stm32mp_ddrctl *ctl) in set_qd1_qd3_update_conditions() argument
35 mmio_setbits_32((uintptr_t)&ctl->dbg1, DDRCTRL_DBG1_DIS_DQ); in set_qd1_qd3_update_conditions()
37 stm32mp_ddr_set_qd3_update_conditions(ctl); in set_qd1_qd3_update_conditions()
40 static void unset_qd1_qd3_update_conditions(struct stm32mp_ddrctl *ctl) in unset_qd1_qd3_update_conditions() argument
42 stm32mp_ddr_unset_qd3_update_conditions(ctl); in unset_qd1_qd3_update_conditions()
44 mmio_clrbits_32((uintptr_t)&ctl->dbg1, DDRCTRL_DBG1_DIS_DQ); in unset_qd1_qd3_update_conditions()
47 static void wait_dfi_init_complete(struct stm32mp_ddrctl *ctl) in wait_dfi_init_complete() argument
54 dfistat = mmio_read_32((uintptr_t)&ctl->dfistat); in wait_dfi_init_complete()
55 VERBOSE("[0x%lx] dfistat = 0x%x ", (uintptr_t)&ctl->dfistat, dfistat); in wait_dfi_init_complete()
62 VERBOSE("[0x%lx] dfistat = 0x%x\n", (uintptr_t)&ctl->dfistat, dfistat); in wait_dfi_init_complete()
[all …]
H A Dstm32mp2_ddr.c286 static void set_dfi_init_complete_en(struct stm32mp_ddrctl *ctl, bool phy_init_done) in set_dfi_init_complete_en() argument
292 stm32mp_ddr_set_qd3_update_conditions(ctl); in set_dfi_init_complete_en()
298 mmio_setbits_32((uintptr_t)&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); in set_dfi_init_complete_en()
301 mmio_clrbits_32((uintptr_t)&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); in set_dfi_init_complete_en()
306 stm32mp_ddr_unset_qd3_update_conditions(ctl); in set_dfi_init_complete_en()
310 static void disable_refresh(struct stm32mp_ddrctl *ctl) in disable_refresh() argument
312 mmio_setbits_32((uintptr_t)&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH); in disable_refresh()
314 stm32mp_ddr_wait_refresh_update_done_ack(ctl); in disable_refresh()
318 mmio_clrbits_32((uintptr_t)&ctl->pwrctl, in disable_refresh()
323 set_dfi_init_complete_en(ctl, false); in disable_refresh()
[all …]
H A Dstm32mp1_ram.c145 priv->ctl = (struct stm32mp_ddrctl *)stm32mp_ddrctrl_base(); in stm32mp1_ddr_probe()
H A Dstm32mp2_ram.c198 priv->ctl = (struct stm32mp_ddrctl *)stm32mp_ddrctrl_base(); in stm32mp2_ddr_probe()
/rk3399_ARM-atf/include/drivers/st/
H A Dstm32mp_ddr.h50 struct stm32mp_ddrctl *ctl; member
71 void stm32mp_ddr_start_sw_done(struct stm32mp_ddrctl *ctl);
72 void stm32mp_ddr_wait_sw_done_ack(struct stm32mp_ddrctl *ctl);
73 void stm32mp_ddr_enable_axi_port(struct stm32mp_ddrctl *ctl);
74 int stm32mp_ddr_disable_axi_port(struct stm32mp_ddrctl *ctl);
75 void stm32mp_ddr_enable_host_interface(struct stm32mp_ddrctl *ctl);
76 void stm32mp_ddr_disable_host_interface(struct stm32mp_ddrctl *ctl);
77 int stm32mp_ddr_sw_selfref_entry(struct stm32mp_ddrctl *ctl);
78 void stm32mp_ddr_sw_selfref_exit(struct stm32mp_ddrctl *ctl);
79 void stm32mp_ddr_set_qd3_update_conditions(struct stm32mp_ddrctl *ctl);
[all …]
H A Dstm32mp2_ddr_helpers.h22 void ddr_activate_controller(struct stm32mp_ddrctl *ctl, bool sr_entry);
/rk3399_ARM-atf/plat/mediatek/drivers/apusys/mt8196/
H A Dapusys_rv_pwr_ctrl.c49 uint8_t usr_bit, enum apu_hw_sem_op ctl, uint32_t timeout, in apu_hw_sema_ctl_per_mbox() argument
55 if (ctl == HW_SEM_GET) in apu_hw_sema_ctl_per_mbox()
57 else if (ctl == HW_SEM_PUT) in apu_hw_sema_ctl_per_mbox()
63 if (ctl == HW_SEM_PUT && ((mmio_read_32(sem_sta_addr) & BIT(usr_bit)) == 0) in apu_hw_sema_ctl_per_mbox()
66 __func__, usr_bit, ctl, sem_sta_addr, mmio_read_32(sem_sta_addr)); in apu_hw_sema_ctl_per_mbox()
72 if (ctl == HW_SEM_PUT) in apu_hw_sema_ctl_per_mbox()
137 int apu_hw_sema_ctl(uint32_t sem_addr, uint8_t usr_bit, uint8_t ctl, uint32_t timeout, in apu_hw_sema_ctl() argument
143 if (ctl == HW_SEM_GET) in apu_hw_sema_ctl()
145 else if (ctl == HW_SEM_PUT) in apu_hw_sema_ctl()
150 if (ctl == HW_SEM_PUT && ((mmio_read_32(sem_addr) & BIT(ctl_bit)) == 0) && !bypass) { in apu_hw_sema_ctl()
[all …]
H A Dapusys_rv_pwr_ctrl.h26 int apu_hw_sema_ctl(uint32_t sem_addr, uint8_t usr_bit, uint8_t ctl, uint32_t timeout,
/rk3399_ARM-atf/bl32/tsp/
H A Dtsp_timer.c20 uint32_t ctl; member
31 uint32_t ctl = 0; in tsp_generic_timer_start() local
38 set_cntp_ctl_enable(ctl); in tsp_generic_timer_start()
39 write_cntps_ctl_el1(ctl); in tsp_generic_timer_start()
77 pcpu_timer_context[linear_id].ctl = read_cntps_ctl_el1(); in tsp_generic_timer_save()
90 write_cntps_ctl_el1(pcpu_timer_context[linear_id].ctl); in tsp_generic_timer_restore()
/rk3399_ARM-atf/fdts/
H A Dstm32mp15-ddr.dtsi11 st,ctl-reg = <
39 st,ctl-timing = <
54 st,ctl-map = <
66 st,ctl-perf = <
H A Dstm32mp25-ddr.dtsi11 st,ctl-reg = <
62 st,ctl-timing = <
85 st,ctl-map = <
100 st,ctl-perf = <
H A Dstm32mp13-ddr.dtsi11 st,ctl-reg = <
39 st,ctl-timing = <
54 st,ctl-map = <
66 st,ctl-perf = <
/rk3399_ARM-atf/plat/mediatek/mt8173/
H A Dplat_pm.c127 uint64_t ctl; in mt_save_generic_timer() local
133 : "=&r" (ctl), "=&r" (val) in mt_save_generic_timer()
140 : "=&r" (val), "=&r" (ctl) in mt_save_generic_timer()
147 : "=&r" (val), "=&r" (ctl) in mt_save_generic_timer()
154 uint64_t ctl; in mt_restore_generic_timer() local
160 : "=&r" (ctl), "=&r" (val) in mt_restore_generic_timer()
167 : "=&r" (val), "=&r" (ctl) in mt_restore_generic_timer()
174 : "=&r" (val), "=&r" (ctl) in mt_restore_generic_timer()
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/dram/
H A Dsuspend.c125 static __pmusramfunc void rkclk_ddr_reset(uint32_t channel, uint32_t ctl, in rkclk_ddr_reset() argument
129 ctl &= 0x1; in rkclk_ddr_reset()
132 CRU_SFTRST_DDR_CTRL(channel, ctl) | in rkclk_ddr_reset()
/rk3399_ARM-atf/include/drivers/nxp/sd/
H A Dsd_mmc.h288 uint32_t ctl; /* Control register */ member
/rk3399_ARM-atf/drivers/nxp/sd/
H A Dsd_mmc.c169 val = esdhc_in32(&mmc->esdhc_regs->ctl) | ESDHC_DCR_SNOOP; in esdhc_init()
170 esdhc_out32(&mmc->esdhc_regs->ctl, val); in esdhc_init()