33 static void set_qd1_qd3_update_conditions(struct stm32mp_ddrctl *ctl)  in set_qd1_qd3_update_conditions()  argument
35 	mmio_setbits_32((uintptr_t)&ctl->dbg1, DDRCTRL_DBG1_DIS_DQ);  in set_qd1_qd3_update_conditions()
37 	stm32mp_ddr_set_qd3_update_conditions(ctl);  in set_qd1_qd3_update_conditions()
40 static void unset_qd1_qd3_update_conditions(struct stm32mp_ddrctl *ctl)  in unset_qd1_qd3_update_conditions()  argument
42 	stm32mp_ddr_unset_qd3_update_conditions(ctl);  in unset_qd1_qd3_update_conditions()
44 	mmio_clrbits_32((uintptr_t)&ctl->dbg1, DDRCTRL_DBG1_DIS_DQ);  in unset_qd1_qd3_update_conditions()
47 static void wait_dfi_init_complete(struct stm32mp_ddrctl *ctl)  in wait_dfi_init_complete()  argument
54 		dfistat = mmio_read_32((uintptr_t)&ctl->dfistat);  in wait_dfi_init_complete()
55 		VERBOSE("[0x%lx] dfistat = 0x%x ", (uintptr_t)&ctl->dfistat, dfistat);  in wait_dfi_init_complete()
62 	VERBOSE("[0x%lx] dfistat = 0x%x\n", (uintptr_t)&ctl->dfistat, dfistat);  in wait_dfi_init_complete()
65 static void disable_dfi_low_power_interface(struct stm32mp_ddrctl *ctl)  in disable_dfi_low_power_interface()  argument
71 	mmio_clrbits_32((uintptr_t)&ctl->dfilpcfg0, DDRCTRL_DFILPCFG0_DFI_LP_EN_SR);  in disable_dfi_low_power_interface()
75 		dfistat = mmio_read_32((uintptr_t)&ctl->dfistat);  in disable_dfi_low_power_interface()
76 		stat = mmio_read_32((uintptr_t)&ctl->stat);  in disable_dfi_low_power_interface()
77 		VERBOSE("[0x%lx] dfistat = 0x%x ", (uintptr_t)&ctl->dfistat, dfistat);  in disable_dfi_low_power_interface()
78 		VERBOSE("[0x%lx] stat = 0x%x ", (uintptr_t)&ctl->stat, stat);  in disable_dfi_low_power_interface()
86 	VERBOSE("[0x%lx] dfistat = 0x%x\n", (uintptr_t)&ctl->dfistat, dfistat);  in disable_dfi_low_power_interface()
87 	VERBOSE("[0x%lx] stat = 0x%x\n", (uintptr_t)&ctl->stat, stat);  in disable_dfi_low_power_interface()
90 void ddr_activate_controller(struct stm32mp_ddrctl *ctl, bool sr_entry)  in ddr_activate_controller()  argument
97 	set_qd1_qd3_update_conditions(ctl);  in ddr_activate_controller()
100 		mmio_setbits_32((uintptr_t)&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_FREQUENCY);  in ddr_activate_controller()
102 		mmio_clrbits_32((uintptr_t)&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_FREQUENCY);  in ddr_activate_controller()
105 	mmio_setbits_32((uintptr_t)&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_START);  in ddr_activate_controller()
106 	mmio_clrbits_32((uintptr_t)&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_START);  in ddr_activate_controller()
108 	wait_dfi_init_complete(ctl);  in ddr_activate_controller()
113 		mmio_clrbits_32((uintptr_t)&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);  in ddr_activate_controller()
115 		mmio_setbits_32((uintptr_t)&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);  in ddr_activate_controller()
120 	unset_qd1_qd3_update_conditions(ctl);  in ddr_activate_controller()