285 		stat = mmio_read_32((uintptr_t)&priv->ctl->stat);  in stm32mp1_wait_operating_mode()
289 			(uintptr_t)&priv->ctl->stat, stat);  in stm32mp1_wait_operating_mode()
319 		(uintptr_t)&priv->ctl->stat, stat);  in stm32mp1_wait_operating_mode()
336 	while ((mmio_read_32((uintptr_t)&priv->ctl->mrstat) &  in stm32mp1_mode_register_write()
349 	mmio_write_32((uintptr_t)&priv->ctl->mrctrl0, mrctrl0);  in stm32mp1_mode_register_write()
351 		(uintptr_t)&priv->ctl->mrctrl0,  in stm32mp1_mode_register_write()
352 		mmio_read_32((uintptr_t)&priv->ctl->mrctrl0), mrctrl0);  in stm32mp1_mode_register_write()
353 	mmio_write_32((uintptr_t)&priv->ctl->mrctrl1, data);  in stm32mp1_mode_register_write()
355 		(uintptr_t)&priv->ctl->mrctrl1,  in stm32mp1_mode_register_write()
356 		mmio_read_32((uintptr_t)&priv->ctl->mrctrl1));  in stm32mp1_mode_register_write()
366 	mmio_write_32((uintptr_t)&priv->ctl->mrctrl0, mrctrl0);  in stm32mp1_mode_register_write()
368 	while ((mmio_read_32((uintptr_t)&priv->ctl->mrstat) &  in stm32mp1_mode_register_write()
374 		(uintptr_t)&priv->ctl->mrctrl0, mrctrl0);  in stm32mp1_mode_register_write()
391 	mmio_setbits_32((uintptr_t)&priv->ctl->dbg1, DDRCTRL_DBG1_DIS_HIF);  in stm32mp1_ddr3_dll_off()
393 		(uintptr_t)&priv->ctl->dbg1,  in stm32mp1_ddr3_dll_off()
394 		mmio_read_32((uintptr_t)&priv->ctl->dbg1));  in stm32mp1_ddr3_dll_off()
405 		dbgcam = mmio_read_32((uintptr_t)&priv->ctl->dbgcam);  in stm32mp1_ddr3_dll_off()
407 			(uintptr_t)&priv->ctl->dbgcam, dbgcam);  in stm32mp1_ddr3_dll_off()
451 	mmio_setbits_32((uintptr_t)&priv->ctl->pwrctl,  in stm32mp1_ddr3_dll_off()
454 		(uintptr_t)&priv->ctl->pwrctl,  in stm32mp1_ddr3_dll_off()
455 		mmio_read_32((uintptr_t)&priv->ctl->pwrctl));  in stm32mp1_ddr3_dll_off()
469 	stm32mp_ddr_start_sw_done(priv->ctl);  in stm32mp1_ddr3_dll_off()
471 	mmio_setbits_32((uintptr_t)&priv->ctl->mstr, DDRCTRL_MSTR_DLL_OFF_MODE);  in stm32mp1_ddr3_dll_off()
473 		(uintptr_t)&priv->ctl->mstr,  in stm32mp1_ddr3_dll_off()
474 		mmio_read_32((uintptr_t)&priv->ctl->mstr));  in stm32mp1_ddr3_dll_off()
476 	stm32mp_ddr_wait_sw_done_ack(priv->ctl);  in stm32mp1_ddr3_dll_off()
509 	stm32mp_ddr_sw_selfref_exit(priv->ctl);  in stm32mp1_ddr3_dll_off()
524 	stm32mp_ddr_enable_host_interface(priv->ctl);  in stm32mp1_ddr3_dll_off()
527 static void stm32mp1_refresh_disable(struct stm32mp_ddrctl *ctl)  in stm32mp1_refresh_disable()  argument
529 	stm32mp_ddr_start_sw_done(ctl);  in stm32mp1_refresh_disable()
531 	mmio_setbits_32((uintptr_t)&ctl->rfshctl3,  in stm32mp1_refresh_disable()
533 	mmio_clrbits_32((uintptr_t)&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN);  in stm32mp1_refresh_disable()
534 	mmio_clrbits_32((uintptr_t)&ctl->dfimisc,  in stm32mp1_refresh_disable()
536 	stm32mp_ddr_wait_sw_done_ack(ctl);  in stm32mp1_refresh_disable()
539 static void stm32mp1_refresh_restore(struct stm32mp_ddrctl *ctl,  in stm32mp1_refresh_restore()  argument
542 	stm32mp_ddr_start_sw_done(ctl);  in stm32mp1_refresh_restore()
544 		mmio_clrbits_32((uintptr_t)&ctl->rfshctl3,  in stm32mp1_refresh_restore()
548 		mmio_setbits_32((uintptr_t)&ctl->pwrctl,  in stm32mp1_refresh_restore()
551 	mmio_setbits_32((uintptr_t)&ctl->dfimisc,  in stm32mp1_refresh_restore()
553 	stm32mp_ddr_wait_sw_done_ack(ctl);  in stm32mp1_refresh_restore()
616 	mmio_clrbits_32((uintptr_t)&priv->ctl->dfimisc,  in stm32mp1_ddr_init()
619 		(uintptr_t)&priv->ctl->dfimisc,  in stm32mp1_ddr_init()
620 		mmio_read_32((uintptr_t)&priv->ctl->dfimisc));  in stm32mp1_ddr_init()
629 		mmio_clrbits_32((uintptr_t)&priv->ctl->mstr,  in stm32mp1_ddr_init()
632 			(uintptr_t)&priv->ctl->mstr,  in stm32mp1_ddr_init()
633 			mmio_read_32((uintptr_t)&priv->ctl->mstr));  in stm32mp1_ddr_init()
640 	mmio_clrsetbits_32((uintptr_t)&priv->ctl->init0,  in stm32mp1_ddr_init()
644 		(uintptr_t)&priv->ctl->init0,  in stm32mp1_ddr_init()
645 		mmio_read_32((uintptr_t)&priv->ctl->init0));  in stm32mp1_ddr_init()
697 	stm32mp_ddr_start_sw_done(priv->ctl);  in stm32mp1_ddr_init()
699 	mmio_setbits_32((uintptr_t)&priv->ctl->dfimisc,  in stm32mp1_ddr_init()
702 		(uintptr_t)&priv->ctl->dfimisc,  in stm32mp1_ddr_init()
703 		mmio_read_32((uintptr_t)&priv->ctl->dfimisc));  in stm32mp1_ddr_init()
705 	stm32mp_ddr_wait_sw_done_ack(priv->ctl);  in stm32mp1_ddr_init()
728 	stm32mp1_refresh_disable(priv->ctl);  in stm32mp1_ddr_init()
754 	stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3,  in stm32mp1_ddr_init()
757 	stm32mp_ddr_enable_axi_port(priv->ctl);  in stm32mp1_ddr_init()