| #
9526ad60 |
| 02-Jun-2025 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "st_fixes" into integration
* changes: fix(st-iwdg): remove num_irq fix(st-drivers): remove useless field in fixed regul fix(st-bsec): remove useless defines in BSEC3
Merge changes from topic "st_fixes" into integration
* changes: fix(st-iwdg): remove num_irq fix(st-drivers): remove useless field in fixed regul fix(st-bsec): remove useless defines in BSEC3 fix(st-bsec): rename OTPSR field fix(st-crypto): do not set IPRST if BUSY flag is present fix(st-ddr): bad refresh update level toggle sequence fix(st-ddr): remove TODO in STM32MP2 driver fix(stm32mp2): correct typo in definition header
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| #
fd5e5e7b |
| 26-Feb-2025 |
Nicolas Le Bayon <nicolas.le.bayon@foss.st.com> |
fix(st-ddr): remove TODO in STM32MP2 driver
Remove useless ddr_get_io_calibration_val service. Other items are deleted as they're useless on STM32MP2 series.
Signed-off-by: Nicolas Le Bayon <nicola
fix(st-ddr): remove TODO in STM32MP2 driver
Remove useless ddr_get_io_calibration_val service. Other items are deleted as they're useless on STM32MP2 series.
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com> Change-Id: I30bb18f156ff6dc06147987654363472a1e0182d
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| #
eaaf26e3 |
| 09-Oct-2024 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes I93de2db1,I880f88b1,I02e2fc75,I48908413,Ie7de9a9f, ... into integration
* changes: feat(st-ddr): add STM32MP2 driver refactor(st-ddr): create generic services refactor(st-ddr): r
Merge changes I93de2db1,I880f88b1,I02e2fc75,I48908413,Ie7de9a9f, ... into integration
* changes: feat(st-ddr): add STM32MP2 driver refactor(st-ddr): create generic services refactor(st-ddr): remove name from stm32mp_ddr_reg_desc refactor(st-ddr): add definition for timeouts and delays feat(st): add stm32mp_is_wakeup_from_standby() feat(stm32mp2): add RETRAM map/unmap capability feat(stm32mp2): add helper to get DDRDBG base address feat(stm32mp2): handle DDR power supplies feat(stm32mp1): handle DDR power supplies
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| #
79629b1a |
| 01-Jul-2021 |
Nicolas Le Bayon <nicolas.le.bayon@st.com> |
feat(st-ddr): add STM32MP2 driver
Add driver to support DDR on STM32MP2 platform. It drives the DDR PHY and its firmware, as well as the DDR controller.
Signed-off-by: Nicolas Le Bayon <nicolas.le.
feat(st-ddr): add STM32MP2 driver
Add driver to support DDR on STM32MP2 platform. It drives the DDR PHY and its firmware, as well as the DDR controller.
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Maxime Méré <maxime.mere@foss.st.com> Change-Id: I93de2db1b9378d5654e76b3bf6f3407d80bc4ca5
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| #
d76d27e9 |
| 22-Aug-2024 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "stm32mp2_bl2_updates" into integration
* changes: feat(stm32mp2): load fw-config file feat(stm32mp2): add fw-config compilation feat(stm32mp2-fdts): add fw-config fil
Merge changes from topic "stm32mp2_bl2_updates" into integration
* changes: feat(stm32mp2): load fw-config file feat(stm32mp2): add fw-config compilation feat(stm32mp2-fdts): add fw-config files for STM32MP257F-EV1 feat(stm32mp2-fdts): add fw-config file feat(stm32mp2-fdts): add clock tree for STM32MP257F-EV1 feat(stm32mp2): enable DDR sub-system clock feat(stm32mp2): add fixed regulators support feat(stm32mp2): print board info feat(stm32mp2): display CPU info feat(stm32mp2): get chip ID feat(stm32mp2): add BL2 boot first steps feat(stm32mp2): add defines for the PWR peripheral feat(stm32mp2-fdts): add SD-card and eMMC support on STM32MP257F-EV1 feat(stm32mp2-fdts): add sdmmc pins definition feat(stm32mp2-fdts): add sdmmc nodes in SoC DT file feat(stm32mp2-fdts): add io_policies feat(stm32mp2-fdts): remove pins-are-numbered
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| #
5e0be8c0 |
| 21-May-2024 |
Yann Gautier <yann.gautier@st.com> |
feat(stm32mp2): enable DDR sub-system clock
Create a DDR helper files, and add a function to enable DDR clocks in RCC_DDRCPCFGR register. Call this ddr_sub_system_clk_init() just before clock driver
feat(stm32mp2): enable DDR sub-system clock
Create a DDR helper files, and add a function to enable DDR clocks in RCC_DDRCPCFGR register. Call this ddr_sub_system_clk_init() just before clock driver init, as it needs to be done before enabling DDR PLL clock (PLL2).
Change-Id: I365d6aa034363d0c036ce2d9f944f077ba86e193 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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