Home
last modified time | relevance | path

Searched refs:TZRAM_BASE (Results 1 – 22 of 22) sorted by relevance

/rk3399_ARM-atf/plat/rockchip/rk3288/include/shared/
H A Dbl32_param.h14 #define TZRAM_BASE (0x0) macro
23 #define BL32_BASE (TZRAM_BASE + 0x40000)
24 #define BL32_LIMIT (TZRAM_BASE + TZRAM_SIZE)
/rk3399_ARM-atf/plat/rockchip/rk3399/include/shared/
H A Dbl31_param.h14 #define TZRAM_BASE (0x0) macro
23 #define BL31_BASE (TZRAM_BASE + 0x40000)
24 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
/rk3399_ARM-atf/plat/mediatek/mt8173/include/
H A Dplatform_def.h74 #define TZRAM_BASE (0x100000) macro
82 #define TZRAM2_BASE (TZRAM_BASE + TZRAM_SIZE)
93 #define BL31_BASE (TZRAM_BASE + 0x1000)
94 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
/rk3399_ARM-atf/plat/rockchip/rk3576/include/
H A Dplatform_def.h70 #define TZRAM_BASE RK_DRAM_BASE macro
79 #define BL31_BASE (TZRAM_BASE + 0x40000)
80 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
/rk3399_ARM-atf/plat/rockchip/rk3588/include/
H A Dplatform_def.h72 #define TZRAM_BASE (0x0) macro
81 #define BL31_BASE (TZRAM_BASE + 0x40000)
82 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
/rk3399_ARM-atf/plat/rockchip/rk3328/include/
H A Dplatform_def.h70 #define TZRAM_BASE (0x0) macro
79 #define BL31_BASE (TZRAM_BASE + 0x40000)
80 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
/rk3399_ARM-atf/plat/rockchip/px30/include/
H A Dplatform_def.h73 #define TZRAM_BASE (0x0) macro
82 #define BL31_BASE (TZRAM_BASE + 0x40000)
83 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
/rk3399_ARM-atf/plat/rockchip/rk3368/include/
H A Dplatform_def.h71 #define TZRAM_BASE (0x0) macro
80 #define BL31_BASE (TZRAM_BASE + 0x40000)
81 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
/rk3399_ARM-atf/plat/rockchip/rk3568/include/
H A Dplatform_def.h72 #define TZRAM_BASE (0x0) macro
81 #define BL31_BASE (TZRAM_BASE + 0x40000)
82 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
/rk3399_ARM-atf/plat/mediatek/mt8192/include/
H A Dplatform_def.h120 #define TZRAM_BASE 0x54600000 macro
131 #define BL31_BASE (TZRAM_BASE + 0x1000)
132 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
/rk3399_ARM-atf/plat/mediatek/mt8186/include/
H A Dplatform_def.h135 #define TZRAM_BASE (0x54600000) macro
146 #define BL31_BASE (TZRAM_BASE + 0x1000)
147 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
/rk3399_ARM-atf/plat/mediatek/mt8195/include/
H A Dplatform_def.h140 #define TZRAM_BASE 0x54600000 macro
151 #define BL31_BASE (TZRAM_BASE + 0x1000)
152 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
/rk3399_ARM-atf/plat/mediatek/mt8189/include/
H A Dplatform_def.h167 #define TZRAM_BASE (0x54600000) macro
178 #define BL31_BASE (TZRAM_BASE + 0x1000)
179 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
/rk3399_ARM-atf/plat/mediatek/mt8188/include/
H A Dplatform_def.h219 #define TZRAM_BASE (0x54600000) macro
230 #define BL31_BASE (TZRAM_BASE + 0x1000)
231 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
/rk3399_ARM-atf/plat/mediatek/mt8196/include/
H A Dplatform_def.h250 #define TZRAM_BASE (0x94600000) macro
261 #define BL31_BASE (TZRAM_BASE + 0x1000)
262 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
/rk3399_ARM-atf/plat/mediatek/mt8183/include/
H A Dplatform_def.h288 #define TZRAM_BASE 0x54600000 macro
299 #define BL31_BASE (TZRAM_BASE + 0x1000)
300 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
/rk3399_ARM-atf/plat/mediatek/mt8173/aarch64/
H A Dplatform_common.c26 MAP_REGION_FLAT(TZRAM_BASE, TZRAM_SIZE,
/rk3399_ARM-atf/plat/mediatek/mt8183/aarch64/
H A Dplatform_common.c23 MAP_REGION_FLAT(TZRAM_BASE, TZRAM_SIZE,
/rk3399_ARM-atf/plat/mediatek/drivers/emi_mpu/mt8188/
H A Demi_mpu.c18 region_info.start = TZRAM_BASE; in set_emi_mpu_regions()
19 region_info.end = TZRAM_BASE + TZRAM_SIZE - 1; in set_emi_mpu_regions()
/rk3399_ARM-atf/plat/rockchip/px30/drivers/secure/
H A Dsecure.c81 secure_ddr_region(0, TZRAM_BASE, TZRAM_SIZE); in sgrf_init()
/rk3399_ARM-atf/plat/rockchip/rk3288/drivers/secure/
H A Dsecure.c163 sgrf_ddr_rgn_config(0, TZRAM_BASE, TZRAM_SIZE); in secure_sgrf_ddr_rgn_init()
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/secure/
H A Dsecure.c165 sgrf_ddr_rgn_config(0, TZRAM_BASE, TZRAM_SIZE); in secure_sgrf_ddr_rgn_init()