16fba6e04STony Xie /* 2c6ee020eSHeiko Stuebner * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. 36fba6e04STony Xie * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 56fba6e04STony Xie */ 66fba6e04STony Xie 71083b2b3SAntonio Nino Diaz #ifndef PLATFORM_DEF_H 81083b2b3SAntonio Nino Diaz #define PLATFORM_DEF_H 96fba6e04STony Xie 106fba6e04STony Xie #include <arch.h> 1109d40e0eSAntonio Nino Diaz #include <lib/utils_def.h> 1209d40e0eSAntonio Nino Diaz #include <plat/common/common_def.h> 1309d40e0eSAntonio Nino Diaz 146fba6e04STony Xie #include <rk3368_def.h> 156fba6e04STony Xie 166fba6e04STony Xie /******************************************************************************* 176fba6e04STony Xie * Platform binary types for linking 186fba6e04STony Xie ******************************************************************************/ 196fba6e04STony Xie #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 206fba6e04STony Xie #define PLATFORM_LINKER_ARCH aarch64 216fba6e04STony Xie 226fba6e04STony Xie /******************************************************************************* 236fba6e04STony Xie * Generic platform constants 246fba6e04STony Xie ******************************************************************************/ 256fba6e04STony Xie 266fba6e04STony Xie /* Size of cacheable stacks */ 272d6f1f01SAntonio Nino Diaz #if defined(IMAGE_BL1) 286fba6e04STony Xie #define PLATFORM_STACK_SIZE 0x440 293d8256b2SMasahiro Yamada #elif defined(IMAGE_BL2) 306fba6e04STony Xie #define PLATFORM_STACK_SIZE 0x400 313d8256b2SMasahiro Yamada #elif defined(IMAGE_BL31) 326fba6e04STony Xie #define PLATFORM_STACK_SIZE 0x800 333d8256b2SMasahiro Yamada #elif defined(IMAGE_BL32) 346fba6e04STony Xie #define PLATFORM_STACK_SIZE 0x440 356fba6e04STony Xie #endif 366fba6e04STony Xie 376fba6e04STony Xie #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 386fba6e04STony Xie 396fba6e04STony Xie #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 40ed7a5636SDeepika Bhavnani #define PLATFORM_SYSTEM_COUNT U(1) 41ed7a5636SDeepika Bhavnani #define PLATFORM_CLUSTER_COUNT U(2) 42ed7a5636SDeepika Bhavnani #define PLATFORM_CLUSTER0_CORE_COUNT U(4) 43ed7a5636SDeepika Bhavnani #define PLATFORM_CLUSTER1_CORE_COUNT U(4) 446fba6e04STony Xie #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 456fba6e04STony Xie PLATFORM_CLUSTER0_CORE_COUNT) 46ed7a5636SDeepika Bhavnani #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 476fba6e04STony Xie #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ 486fba6e04STony Xie PLATFORM_CLUSTER_COUNT + \ 496fba6e04STony Xie PLATFORM_CORE_COUNT) 506fba6e04STony Xie 51*198a705fSPhilipp Tomsich #define PLAT_RK_CLST_TO_CPUID_SHIFT 6 529ec78bdfSTony Xie 536fba6e04STony Xie #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 546fba6e04STony Xie 556fba6e04STony Xie /* 566fba6e04STony Xie * This macro defines the deepest retention state possible. A higher state 576fba6e04STony Xie * id will represent an invalid or a power down state. 586fba6e04STony Xie */ 591083b2b3SAntonio Nino Diaz #define PLAT_MAX_RET_STATE U(1) 606fba6e04STony Xie 616fba6e04STony Xie /* 626fba6e04STony Xie * This macro defines the deepest power down states possible. Any state ID 636fba6e04STony Xie * higher than this is invalid. 646fba6e04STony Xie */ 651083b2b3SAntonio Nino Diaz #define PLAT_MAX_OFF_STATE U(2) 666fba6e04STony Xie 676fba6e04STony Xie /******************************************************************************* 686fba6e04STony Xie * Platform memory map related constants 696fba6e04STony Xie ******************************************************************************/ 70c6ee020eSHeiko Stuebner /* TF text, ro, rw, Size: 1MB */ 716fba6e04STony Xie #define TZRAM_BASE (0x0) 72c6ee020eSHeiko Stuebner #define TZRAM_SIZE (0x100000) 736fba6e04STony Xie 746fba6e04STony Xie /******************************************************************************* 756fba6e04STony Xie * BL31 specific defines. 766fba6e04STony Xie ******************************************************************************/ 776fba6e04STony Xie /* 786fba6e04STony Xie * Put BL3-1 at the top of the Trusted RAM 796fba6e04STony Xie */ 800aad563cSKever Yang #define BL31_BASE (TZRAM_BASE + 0x40000) 816fba6e04STony Xie #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 826fba6e04STony Xie 836fba6e04STony Xie /******************************************************************************* 846fba6e04STony Xie * Platform specific page table and MMU setup constants 856fba6e04STony Xie ******************************************************************************/ 862d6f1f01SAntonio Nino Diaz #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 872d6f1f01SAntonio Nino Diaz #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 886fba6e04STony Xie #define MAX_XLAT_TABLES 8 89a7e0be55SHeiko Stuebner #define MAX_MMAP_REGIONS 20 906fba6e04STony Xie 916fba6e04STony Xie /******************************************************************************* 926fba6e04STony Xie * Declarations and constants to access the mailboxes safely. Each mailbox is 936fba6e04STony Xie * aligned on the biggest cache line size in the platform. This is known only 946fba6e04STony Xie * to the platform as it might have a combination of integrated and external 956fba6e04STony Xie * caches. Such alignment ensures that two maiboxes do not sit on the same cache 966fba6e04STony Xie * line at any cache level. They could belong to different cpus/clusters & 976fba6e04STony Xie * get written while being protected by different locks causing corruption of 986fba6e04STony Xie * a valid mailbox address. 996fba6e04STony Xie ******************************************************************************/ 1006fba6e04STony Xie #define CACHE_WRITEBACK_SHIFT 6 1016fba6e04STony Xie #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 1026fba6e04STony Xie 1036fba6e04STony Xie /* 1046fba6e04STony Xie * Define GICD and GICC and GICR base 1056fba6e04STony Xie */ 1066fba6e04STony Xie #define PLAT_RK_GICD_BASE RK3368_GICD_BASE 1076fba6e04STony Xie #define PLAT_RK_GICC_BASE RK3368_GICC_BASE 1086fba6e04STony Xie 1090957b9b2SChristoph Müllner #define PLAT_RK_UART_BASE UART2_BASE 1106fba6e04STony Xie #define PLAT_RK_UART_CLOCK RK3368_UART_CLOCK 1116fba6e04STony Xie #define PLAT_RK_UART_BAUDRATE RK3368_BAUDRATE 1126fba6e04STony Xie 1136fba6e04STony Xie #define PLAT_RK_CCI_BASE CCI400_BASE 1146fba6e04STony Xie 1156fba6e04STony Xie #define PLAT_RK_PRIMARY_CPU 0x0 1166fba6e04STony Xie 117bc5c3007SLin Huang #define PSRAM_DO_DDR_RESUME 0 11884597b57SLin Huang #define PSRAM_CHECK_WAKEUP_CPU 0 119bc5c3007SLin Huang 1201083b2b3SAntonio Nino Diaz #endif /* PLATFORM_DEF_H */ 121