| /rk3399_ARM-atf/plat/hisilicon/hikey/ |
| H A D | hikey_pm.c | 64 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) in hikey_pwr_domain_on_finish()
88 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in hikey_pwr_domain_off()
104 if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) in hikey_pwr_domain_suspend()
107 if (CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in hikey_pwr_domain_suspend()
114 if (SYSTEM_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) in hikey_pwr_domain_suspend()
119 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in hikey_pwr_domain_suspend()
124 if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in hikey_pwr_domain_suspend()
139 if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) in hikey_pwr_domain_suspend_finish()
148 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) in hikey_pwr_domain_suspend_finish()
153 if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in hikey_pwr_domain_suspend_finish()
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| /rk3399_ARM-atf/plat/rockchip/common/ |
| H A D | plat_pm.c | 156 PLAT_MAX_OFF_STATE; in rockchip_validate_power_state()
175 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in rockchip_get_sys_suspend_power_state()
220 assert(RK_CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE); in rockchip_pwr_domain_off()
224 if (RK_CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) in rockchip_pwr_domain_off()
247 if (RK_CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) in rockchip_pwr_domain_suspend()
253 if (RK_SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) in rockchip_pwr_domain_suspend()
259 if (RK_CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) in rockchip_pwr_domain_suspend()
262 if (RK_SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) in rockchip_pwr_domain_suspend()
284 assert(RK_CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE); in rockchip_pwr_domain_on_finish()
296 if (RK_CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in rockchip_pwr_domain_on_finish()
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| /rk3399_ARM-atf/plat/nxp/common/psci/ |
| H A D | plat_psci.c | 175 if (state->pwr_domain_state[PLAT_MAX_LVL] == PLAT_MAX_OFF_STATE) { in _pwr_suspend()
195 PLAT_MAX_OFF_STATE) { in _pwr_suspend()
216 else if (state->pwr_domain_state[PLAT_CORE_LVL] == PLAT_MAX_OFF_STATE) { in _pwr_suspend()
248 if (state->pwr_domain_state[PLAT_MAX_LVL] == PLAT_MAX_OFF_STATE) { in _pwr_suspend_finish()
272 PLAT_MAX_OFF_STATE) { in _pwr_suspend_finish()
297 else if (state->pwr_domain_state[PLAT_CORE_LVL] == PLAT_MAX_OFF_STATE) { in _pwr_suspend_finish()
349 PLAT_MAX_OFF_STATE; in _pwr_state_validate()
357 PLAT_MAX_OFF_STATE; in _pwr_state_validate()
365 PLAT_MAX_OFF_STATE; in _pwr_state_validate()
375 PLAT_MAX_OFF_STATE; in _pwr_state_validate()
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| /rk3399_ARM-atf/plat/renesas/rcar_gen4/ |
| H A D | plat_pm.c | 81 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in rcar_pwr_domain_off()
92 if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) { in rcar_pwr_domain_suspend()
99 if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in rcar_pwr_domain_suspend()
105 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in rcar_pwr_domain_suspend()
117 if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in rcar_pwr_domain_suspend_finish()
124 if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in rcar_pwr_domain_suspend_finish()
154 if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) in rcar_pwr_domain_pwr_down_wfi()
172 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in rcar_validate_power_state()
195 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in rcar_get_sys_suspend_power_state()
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| /rk3399_ARM-atf/plat/renesas/rcar_gen5/ |
| H A D | plat_pm.c | 87 if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) { in rcar_pwr_domain_suspend()
94 if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in rcar_pwr_domain_suspend()
106 if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in rcar_pwr_domain_suspend_finish()
114 if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in rcar_pwr_domain_suspend_finish()
152 if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in rcar_pwr_domain_pwr_down_wfi()
177 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in rcar_validate_power_state()
193 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in rcar_get_sys_suspend_power_state()
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| /rk3399_ARM-atf/plat/imx/common/ |
| H A D | imx8_psci.c | 43 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in imx_validate_power_state()
47 req_state->pwr_domain_state[MPIDR_AFFLVL1] = PLAT_MAX_OFF_STATE; in imx_validate_power_state()
59 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in imx_get_sys_suspend_power_state()
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| /rk3399_ARM-atf/plat/renesas/common/ |
| H A D | plat_pm.c | 83 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) in rcar_pwr_domain_on_finish()
106 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in rcar_pwr_domain_off()
120 if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) in rcar_pwr_domain_suspend()
128 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in rcar_pwr_domain_suspend()
141 if (SYSTEM_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) in rcar_pwr_domain_suspend_finish()
164 if (SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) in rcar_pwr_domain_pwr_down_wfi()
268 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in rcar_validate_power_state()
287 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in rcar_get_sys_suspend_power_state()
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| /rk3399_ARM-atf/plat/mediatek/topology/group_4_3_1/ |
| H A D | topology_conf.mk | 10 PLAT_MAX_OFF_STATE := 2
11 $(eval $(call add_defined_option,PLAT_MAX_OFF_STATE))
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| /rk3399_ARM-atf/plat/hisilicon/hikey960/ |
| H A D | hikey960_pm.c | 85 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) in hikey960_pwr_domain_on_finish()
164 PLAT_MAX_OFF_STATE; in hikey960_validate_power_state()
195 if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) in hikey960_pwr_domain_suspend()
198 if (CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in hikey960_pwr_domain_suspend()
216 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in hikey960_pwr_domain_suspend()
272 if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) in hikey960_pwr_domain_suspend_finish()
294 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in hikey960_get_sys_suspend_power_state()
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| /rk3399_ARM-atf/plat/mediatek/include/armv9/ |
| H A D | arch_def.h | 18 #ifndef PLAT_MAX_OFF_STATE
19 #define PLAT_MAX_OFF_STATE MPIDR_AFFLVL2 macro
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| /rk3399_ARM-atf/plat/nxp/soc-ls1028a/include/ |
| H A D | soc.h | 132 #define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1) macro
133 #define LS_LOCAL_STATE_OFF PLAT_MAX_OFF_STATE
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| /rk3399_ARM-atf/plat/hisilicon/poplar/ |
| H A D | plat_pm.c | 77 PLAT_MAX_OFF_STATE); in poplar_pwr_domain_on_finish()
126 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in poplar_validate_power_state()
152 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in poplar_get_sys_suspend_power_state()
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| /rk3399_ARM-atf/plat/ti/k3/common/ |
| H A D | k3_psci.c | 91 assert(CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE); in k3_pwr_domain_off()
107 if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { in k3_pwr_domain_off()
137 if (CLUSTER_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) in k3_pwr_domain_off()
297 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in k3_get_sys_suspend_power_state()
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| /rk3399_ARM-atf/plat/mediatek/include/armv8_2/ |
| H A D | arch_def.h | 13 #define PLAT_MAX_OFF_STATE (2) macro
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| /rk3399_ARM-atf/plat/nxp/soc-ls1088a/include/ |
| H A D | soc.h | 214 #define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1) macro
215 #define LS_LOCAL_STATE_OFF PLAT_MAX_OFF_STATE
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| /rk3399_ARM-atf/plat/xilinx/zynqmp/ |
| H A D | plat_psci.c | 227 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in zynqmp_validate_power_state()
239 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; in zynqmp_get_sys_suspend_power_state()
240 req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE; in zynqmp_get_sys_suspend_power_state()
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| /rk3399_ARM-atf/plat/nxp/soc-ls1043a/include/ |
| H A D | soc.h | 210 #define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1) macro
211 #define LS_LOCAL_STATE_OFF PLAT_MAX_OFF_STATE
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| /rk3399_ARM-atf/plat/xilinx/versal/ |
| H A D | plat_psci.c | 289 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in versal_validate_power_state()
307 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; in versal_get_sys_suspend_power_state()
308 req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE; in versal_get_sys_suspend_power_state()
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| /rk3399_ARM-atf/plat/imx/imx9/common/ |
| H A D | imx9_psci_common.c | 57 CORE_PWR_STATE(req_state) = PLAT_MAX_OFF_STATE; in imx_validate_power_state()
62 CORE_PWR_STATE(req_state) = PLAT_MAX_OFF_STATE; in imx_validate_power_state()
270 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in imx_get_sys_suspend_power_state()
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| /rk3399_ARM-atf/plat/hisilicon/hikey/include/ |
| H A D | platform_def.h | 40 #define PLAT_MAX_OFF_STATE U(2) macro
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| /rk3399_ARM-atf/plat/amlogic/gxl/include/ |
| H A D | platform_def.h | 32 #define PLAT_MAX_OFF_STATE U(2) macro
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| /rk3399_ARM-atf/plat/amlogic/g12a/include/ |
| H A D | platform_def.h | 32 #define PLAT_MAX_OFF_STATE U(2) macro
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| /rk3399_ARM-atf/plat/amlogic/gxbb/include/ |
| H A D | platform_def.h | 35 #define PLAT_MAX_OFF_STATE U(2) macro
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| /rk3399_ARM-atf/plat/amlogic/axg/include/ |
| H A D | platform_def.h | 32 #define PLAT_MAX_OFF_STATE U(2) macro
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| /rk3399_ARM-atf/plat/rockchip/rk3288/include/ |
| H A D | platform_def.h | 62 #define PLAT_MAX_OFF_STATE U(2) macro
|