1780e3f24SHeiko Stuebner /* 2*ed7a5636SDeepika Bhavnani * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. 3780e3f24SHeiko Stuebner * 4780e3f24SHeiko Stuebner * SPDX-License-Identifier: BSD-3-Clause 5780e3f24SHeiko Stuebner */ 6780e3f24SHeiko Stuebner 7780e3f24SHeiko Stuebner #ifndef PLATFORM_DEF_H 8780e3f24SHeiko Stuebner #define PLATFORM_DEF_H 9780e3f24SHeiko Stuebner 10780e3f24SHeiko Stuebner #include <arch.h> 11780e3f24SHeiko Stuebner #include <lib/utils_def.h> 12780e3f24SHeiko Stuebner #include <plat/common/common_def.h> 13780e3f24SHeiko Stuebner 14780e3f24SHeiko Stuebner #include <bl32_param.h> 15780e3f24SHeiko Stuebner #include <rk3288_def.h> 16780e3f24SHeiko Stuebner 17780e3f24SHeiko Stuebner /******************************************************************************* 18780e3f24SHeiko Stuebner * Platform binary types for linking 19780e3f24SHeiko Stuebner ******************************************************************************/ 20780e3f24SHeiko Stuebner #define PLATFORM_LINKER_FORMAT "elf32-littlearm" 21780e3f24SHeiko Stuebner #define PLATFORM_LINKER_ARCH arm 22780e3f24SHeiko Stuebner 23780e3f24SHeiko Stuebner /******************************************************************************* 24780e3f24SHeiko Stuebner * Generic platform constants 25780e3f24SHeiko Stuebner ******************************************************************************/ 26780e3f24SHeiko Stuebner 27780e3f24SHeiko Stuebner /* Size of cacheable stacks */ 28780e3f24SHeiko Stuebner #if defined(IMAGE_BL1) 29780e3f24SHeiko Stuebner #define PLATFORM_STACK_SIZE 0x440 30780e3f24SHeiko Stuebner #elif defined(IMAGE_BL2) 31780e3f24SHeiko Stuebner #define PLATFORM_STACK_SIZE 0x400 32780e3f24SHeiko Stuebner #elif defined(IMAGE_BL32) 33780e3f24SHeiko Stuebner #define PLATFORM_STACK_SIZE 0x800 34780e3f24SHeiko Stuebner #endif 35780e3f24SHeiko Stuebner 36780e3f24SHeiko Stuebner #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 37780e3f24SHeiko Stuebner 38780e3f24SHeiko Stuebner #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 39*ed7a5636SDeepika Bhavnani #define PLATFORM_SYSTEM_COUNT U(1) 40*ed7a5636SDeepika Bhavnani #define PLATFORM_CLUSTER_COUNT U(1) 41*ed7a5636SDeepika Bhavnani #define PLATFORM_CLUSTER0_CORE_COUNT U(4) 42780e3f24SHeiko Stuebner #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) 43*ed7a5636SDeepika Bhavnani #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 44780e3f24SHeiko Stuebner #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ 45780e3f24SHeiko Stuebner PLATFORM_CLUSTER_COUNT + \ 46780e3f24SHeiko Stuebner PLATFORM_CORE_COUNT) 47780e3f24SHeiko Stuebner 48780e3f24SHeiko Stuebner #define PLAT_RK_CLST_TO_CPUID_SHIFT 6 49780e3f24SHeiko Stuebner 50780e3f24SHeiko Stuebner #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 51780e3f24SHeiko Stuebner 52780e3f24SHeiko Stuebner /* 53780e3f24SHeiko Stuebner * This macro defines the deepest retention state possible. A higher state 54780e3f24SHeiko Stuebner * id will represent an invalid or a power down state. 55780e3f24SHeiko Stuebner */ 56780e3f24SHeiko Stuebner #define PLAT_MAX_RET_STATE U(1) 57780e3f24SHeiko Stuebner 58780e3f24SHeiko Stuebner /* 59780e3f24SHeiko Stuebner * This macro defines the deepest power down states possible. Any state ID 60780e3f24SHeiko Stuebner * higher than this is invalid. 61780e3f24SHeiko Stuebner */ 62780e3f24SHeiko Stuebner #define PLAT_MAX_OFF_STATE U(2) 63780e3f24SHeiko Stuebner 64780e3f24SHeiko Stuebner /******************************************************************************* 65780e3f24SHeiko Stuebner * Platform specific page table and MMU setup constants 66780e3f24SHeiko Stuebner ******************************************************************************/ 67780e3f24SHeiko Stuebner #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 68780e3f24SHeiko Stuebner #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 69780e3f24SHeiko Stuebner #define MAX_XLAT_TABLES 8 70780e3f24SHeiko Stuebner #define MAX_MMAP_REGIONS 18 71780e3f24SHeiko Stuebner 72780e3f24SHeiko Stuebner /******************************************************************************* 73780e3f24SHeiko Stuebner * Declarations and constants to access the mailboxes safely. Each mailbox is 74780e3f24SHeiko Stuebner * aligned on the biggest cache line size in the platform. This is known only 75780e3f24SHeiko Stuebner * to the platform as it might have a combination of integrated and external 76780e3f24SHeiko Stuebner * caches. Such alignment ensures that two maiboxes do not sit on the same cache 77780e3f24SHeiko Stuebner * line at any cache level. They could belong to different cpus/clusters & 78780e3f24SHeiko Stuebner * get written while being protected by different locks causing corruption of 79780e3f24SHeiko Stuebner * a valid mailbox address. 80780e3f24SHeiko Stuebner ******************************************************************************/ 81780e3f24SHeiko Stuebner #define CACHE_WRITEBACK_SHIFT 6 82780e3f24SHeiko Stuebner #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 83780e3f24SHeiko Stuebner 84780e3f24SHeiko Stuebner /* 85780e3f24SHeiko Stuebner * Define GICD and GICC and GICR base 86780e3f24SHeiko Stuebner */ 87780e3f24SHeiko Stuebner #define PLAT_RK_GICD_BASE RK3288_GICD_BASE 88780e3f24SHeiko Stuebner #define PLAT_RK_GICC_BASE RK3288_GICC_BASE 89780e3f24SHeiko Stuebner 900957b9b2SChristoph Müllner #define PLAT_RK_UART_BASE UART2_BASE 91780e3f24SHeiko Stuebner #define PLAT_RK_UART_CLOCK RK3288_UART_CLOCK 92780e3f24SHeiko Stuebner #define PLAT_RK_UART_BAUDRATE RK3288_BAUDRATE 93780e3f24SHeiko Stuebner 94780e3f24SHeiko Stuebner /* ClusterId is always 0x5 on rk3288, filter it */ 95780e3f24SHeiko Stuebner #define PLAT_RK_MPIDR_CLUSTER_MASK 0 96780e3f24SHeiko Stuebner #define PLAT_RK_PRIMARY_CPU 0x0 97780e3f24SHeiko Stuebner 98780e3f24SHeiko Stuebner #define PSRAM_DO_DDR_RESUME 0 99780e3f24SHeiko Stuebner #define PSRAM_CHECK_WAKEUP_CPU 0 100780e3f24SHeiko Stuebner 101780e3f24SHeiko Stuebner #endif /* PLATFORM_DEF_H */ 102