Home
last modified time | relevance | path

Searched refs:CTX_GPREG_X2 (Results 1 – 22 of 22) sorted by relevance

/rk3399_ARM-atf/lib/cpus/aarch64/
H A Dwa_cve_2022_23960_bhb.S26 str x2, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
38 ldr x2, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
H A Dwa_cve_2017_5715_bpiall.S27 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
342 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
346 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
350 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
366 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
H A Dcortex_a76.S48 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
70 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
H A Dneoverse_n1.S274 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t186/drivers/mce/
H A Dmce.c210 write_ctx_reg(gp_regs, CTX_GPREG_X2, (ret64)); in mce_command_handler()
253 write_ctx_reg(gp_regs, CTX_GPREG_X2, ((ret64 == arg0) ? in mce_command_handler()
267 write_ctx_reg(gp_regs, CTX_GPREG_X2, (ret64 >> 32ULL)); in mce_command_handler()
300 write_ctx_reg(gp_regs, CTX_GPREG_X2, (arg1)); in mce_command_handler()
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/
H A Dplat_sip_calls.c69 write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X2, per[1]); in plat_sip_handler()
/rk3399_ARM-atf/services/std_svc/spm/el3_spmc/
H A Dspmc_pm.c33 write_ctx_reg(gpregs, CTX_GPREG_X2, FFA_FWK_MSG_BIT | in spmc_build_pm_message()
186 resp = read_ctx_reg(gpregs_ctx, CTX_GPREG_X2); in spmc_send_pm_msg()
H A Dspmc_main.c316 uint64_t x2 = SMC_GET_GP(handle, CTX_GPREG_X2); in direct_msg_validate_lp_resp()
/rk3399_ARM-atf/plat/nvidia/tegra/common/
H A Dtegra_fiq_glue.c143 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X2), (val)); in tegra_fiq_get_intr_context()
/rk3399_ARM-atf/include/arch/aarch64/
H A Dsmccc_helpers.h45 write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X2), (_x2)); \
112 _x2 = read_ctx_reg(regs, CTX_GPREG_X2); \
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t186/
H A Dplat_sip_calls.c148 CTX_GPREG_X2, (ref_clk_ctr)); in plat_sip_handler()
/rk3399_ARM-atf/services/std_svc/spmd/
H A Dspmd_pm.c164 CTX_GPREG_X2); in spmd_cpu_off_handler()
H A Dspmd_logical_sp.c145 write_ctx_reg(gpregs, CTX_GPREG_X2, x2); in spmd_build_direct_message_req()
160 retval->arg2 = read_ctx_reg(gpregs, CTX_GPREG_X2); in spmd_encode_ctx_to_ffa_value()
201 write_ctx_reg(gpregs, CTX_GPREG_X2, arg2); in spmd_build_ffa_info_get_regs()
H A Dspmd_main.c116 write_ctx_reg(gpregs, CTX_GPREG_X2, BIT(31) | target_func); in spmd_build_spmc_message()
270 write_ctx_reg(gpregs, CTX_GPREG_X2, 0); in spmd_secure_interrupt_handler()
1078 (SMC_GET_GP(gpregs, CTX_GPREG_X2) != in spmd_smc_handler()
/rk3399_ARM-atf/bl31/aarch64/
H A Druntime_exceptions.S603 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
622 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
/rk3399_ARM-atf/services/std_svc/spm/spm_mm/
H A Dspm_mm_main.c185 write_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X2, x2); in spm_mm_sp_call()
H A Dspm_mm_setup.c326 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2, in spm_sp_setup()
/rk3399_ARM-atf/plat/qti/qtiseclib/src/
H A Dqtiseclib_cb_interface.c152 qti_ns_ctx->x2 = read_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2); in qtiseclib_cb_get_ns_ctx()
/rk3399_ARM-atf/include/lib/el3_runtime/aarch64/
H A Dcontext.h40 #define CTX_GPREG_X2 U(0x10) macro
/rk3399_ARM-atf/lib/el3_runtime/aarch64/
H A Dcontext.S354 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
493 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
/rk3399_ARM-atf/docs/security_advisories/
H A Dsecurity-advisory-tfv-8.rst50 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
/rk3399_ARM-atf/services/std_svc/sdei/
H A Dsdei_intr_mgmt.c290 SMC_SET_GP(ctx, CTX_GPREG_X2, disp_ctx->elr_el3); in setup_ns_dispatch()