| #
ab471aeb |
| 29-Oct-2025 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge "fix(security): add clrbhb support" into integration
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| #
d6affea1 |
| 02-Oct-2025 |
Govindraj Raja <govindraj.raja@arm.com> |
fix(security): add clrbhb support
TF-A mitigates spectre-bhb(CVE-2022-23960) issue with loop
workaround based on - https://developer.arm.com/documentation/110280/latest/
On platforms that support `
fix(security): add clrbhb support
TF-A mitigates spectre-bhb(CVE-2022-23960) issue with loop
workaround based on - https://developer.arm.com/documentation/110280/latest/
On platforms that support `clrbhb` instruction it is recommended to
use `clrbhb` instruction instead of the loop workaround.
Ref- https://developer.arm.com/documentation/102898/0108/
Change-Id: Ie6e56e96378503456a1617d5e5d51bc64c2e0f0b
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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| #
72e8f245 |
| 08-Aug-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "chore: update to use Arm word across TF-A" into integration
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| #
4c700c15 |
| 01-Aug-2023 |
Govindraj Raja <govindraj.raja@arm.com> |
chore: update to use Arm word across TF-A
Align entire TF-A to use Arm in copyright header.
Change-Id: Ief9992169efdab61d0da6bd8c5180de7a4bc2244
Signed-off-by: Govindraj Raja <govindraj.raja@arm.co
chore: update to use Arm word across TF-A
Align entire TF-A to use Arm in copyright header.
Change-Id: Ief9992169efdab61d0da6bd8c5180de7a4bc2244
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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| #
52a79b0e |
| 26-Oct-2022 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge "fix(security): optimisations for CVE-2022-23960" into integration
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| #
e74d6581 |
| 13-Oct-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(security): optimisations for CVE-2022-23960
Optimised the loop workaround for Spectre_BHB mitigation:
1. use of speculation barrier for cores implementing SB instruction.
2. use str/ldr instead
fix(security): optimisations for CVE-2022-23960
Optimised the loop workaround for Spectre_BHB mitigation:
1. use of speculation barrier for cores implementing SB instruction.
2. use str/ldr instead of stp/ldp as the loop uses only X2 register.
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I8ac53ea1e42407ad8004c1d59c05f791011f195d
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| #
29ba22e8 |
| 12-Mar-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(security): workaround for CVE-2022-23960" into integration
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| #
1fe4a9d1 |
| 18-Jan-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(security): workaround for CVE-2022-23960
Implements the loop workaround for Cortex-A77, Cortex-A78,
Cortex-A710, Cortex-X2, Neoverse N1, Neoverse N2 and Neoverse V1
CPUs.
Signed-off-by: Bipin R
fix(security): workaround for CVE-2022-23960
Implements the loop workaround for Cortex-A77, Cortex-A78,
Cortex-A710, Cortex-X2, Neoverse N1, Neoverse N2 and Neoverse V1
CPUs.
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I11d342df7a2068a15e18f4974c645af3b341235b
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