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Searched refs:CRU_BASE (Results 1 – 25 of 34) sorted by relevance

12

/rk3399_ARM-atf/plat/rockchip/rk3368/drivers/soc/
H A Dsoc.c43 MAP_REGION_FLAT(CRU_BASE, CRU_SIZE,
90 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1), in sgrf_init()
93 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4), in sgrf_init()
99 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1), (RST_DMA1_MSK << 16)); in sgrf_init()
101 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4), (RST_DMA2_MSK << 16)); in sgrf_init()
127 plls_con[pll_id][0] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 0)); in plls_suspend()
128 plls_con[pll_id][1] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 1)); in plls_suspend()
129 plls_con[pll_id][2] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 2)); in plls_suspend()
130 plls_con[pll_id][3] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 3)); in plls_suspend()
132 mmio_write_32(CRU_BASE + PLL_CONS((pll_id), 3), PLL_SLOW_BITS); in plls_suspend()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3328/drivers/pmu/
H A Dpmu.c195 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(CPLL_ID)); in rockchip_soc_soft_reset()
196 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(GPLL_ID)); in rockchip_soc_soft_reset()
197 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(NPLL_ID)); in rockchip_soc_soft_reset()
198 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(APLL_ID)); in rockchip_soc_soft_reset()
201 mmio_write_32(CRU_BASE + CRU_GLB_SRST_FST, CRU_GLB_SRST_FST_VALUE); in rockchip_soc_soft_reset()
255 mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(i)); in clks_gating_suspend()
256 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), in clks_gating_suspend()
266 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), in clks_gating_resume()
275 if (mmio_read_32(CRU_BASE + PLL_CONS(pll_id, 1)) & in pm_pll_wait_lock()
286 mmio_write_32(CRU_BASE + PLL_CONS(pll_id, 1), in pll_pwr_dwn()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3568/drivers/scmi/
H A Drk3568_clk.c297 mmio_write_32(CRU_BASE + RK3568_CLK_SEL(0), in rk3568_apll_set_rate()
302 mmio_write_32(CRU_BASE + 0xc0, in rk3568_apll_set_rate()
307 mmio_write_32(CRU_BASE + RK3568_PLLCON(0), in rk3568_apll_set_rate()
311 mmio_write_32(CRU_BASE + RK3568_PLLCON(0), in rk3568_apll_set_rate()
315 mmio_write_32(CRU_BASE + RK3568_PLLCON(1), in rk3568_apll_set_rate()
319 mmio_write_32(CRU_BASE + RK3568_PLLCON(1), in rk3568_apll_set_rate()
323 mmio_write_32(CRU_BASE + RK3568_PLLCON(1), in rk3568_apll_set_rate()
330 if (mmio_read_32(CRU_BASE + RK3568_PLLCON(1)) & in rk3568_apll_set_rate()
340 mmio_write_32(CRU_BASE + 0xc0, in rk3568_apll_set_rate()
353 mode = (mmio_read_32(CRU_BASE + 0xc0) >> RK3568_PLL_MODE_SHIFT) & in rk3568_apll_get_rate()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3288/drivers/soc/
H A Dsoc.c47 MAP_REGION_FLAT(CRU_BASE, CRU_SIZE,
109 pll[0] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 0)); in pll_save()
110 pll[1] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 1)); in pll_save()
111 pll[2] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 2)); in pll_save()
112 pll[3] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 3)); in pll_save()
121 slp_data.pll_mode = mmio_read_32(CRU_BASE + PLL_MODE_CON); in clk_plls_suspend()
133 mmio_write_32(CRU_BASE + PLL_MODE_CON, 0xf3030000); in clk_plls_suspend()
139 mmio_write_32(CRU_BASE + PLL_MODE_CON, in clk_plls_resume()
149 mmio_read_32(CRU_BASE + CRU_CLKGATES_CON(i)); in clk_gate_con_save()
157 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), REG_SOC_WMSK); in clk_gate_con_disable()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/soc/
H A Dsoc.c58 mmio_write_32((CRU_BASE + in set_pll_slow_mode()
67 mmio_write_32(CRU_BASE + in set_pll_normal_mode()
77 mmio_write_32(CRU_BASE + in set_pll_bypass()
126 mmio_write_32((CRU_BASE + CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); in restore_pll()
128 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 0), src[0] | REG_SOC_WMSK); in restore_pll()
129 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 1), src[1] | REG_SOC_WMSK); in restore_pll()
130 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 2), src[2]); in restore_pll()
131 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 4), src[4] | REG_SOC_WMSK); in restore_pll()
132 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 5), src[5] | REG_SOC_WMSK); in restore_pll()
135 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), src[3] | REG_SOC_WMSK); in restore_pll()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/m0/src/
H A Ddram.c43 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_SLOW_MODE)); in ddr_set_pll()
45 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_POWER_DOWN(1)); in ddr_set_pll()
46 mmio_write_32(CRU_BASE + CRU_DPLL_CON0, in ddr_set_pll()
48 mmio_write_32(CRU_BASE + CRU_DPLL_CON1, in ddr_set_pll()
50 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_POWER_DOWN(0)); in ddr_set_pll()
52 while ((mmio_read_32(CRU_BASE + CRU_DPLL_CON2) & (1u << 31)) == 0) in ddr_set_pll()
55 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_NORMAL_MODE)); in ddr_set_pll()
/rk3399_ARM-atf/plat/rockchip/px30/drivers/soc/
H A Dsoc.c52 mmio_read_32(CRU_BASE + CRU_CLKGATES_CON(i)); in clk_gate_con_save()
64 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), in clk_gate_con_restore()
78 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), in clk_gate_con_disable()
91 tmp = mmio_read_32(CRU_BASE + CRU_GLB_RST_CON); in soc_reset_config_all()
93 mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, tmp); in soc_reset_config_all()
109 tmp = mmio_read_32(CRU_BASE + CRU_GLB_RST_CON); in px30_soc_reset_config()
111 mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, tmp); in px30_soc_reset_config()
113 tmp = mmio_read_32(CRU_BASE + CRU_GLB_CNT_TH); in px30_soc_reset_config()
116 mmio_write_32(CRU_BASE + CRU_GLB_CNT_TH, tmp); in px30_soc_reset_config()
/rk3399_ARM-atf/plat/rockchip/rk3576/drivers/soc/
H A Dsoc.c47 uint32_t cru_sel55 = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(55)); in clear_glb_reset_status()
50 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(55), in clear_glb_reset_status()
54 mmio_write_32(CRU_BASE + CRU_GLB_RST_ST, 0xffff); in clear_glb_reset_status()
57 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(55), in clear_glb_reset_status()
68 glb_rst_st = mmio_read_32(CRU_BASE + CRU_GLB_RST_ST_NCLR) & VALID_GLB_RST_MSK; in print_glb_reset_status()
92 mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, 0xffdf); in system_reset_init()
/rk3399_ARM-atf/plat/rockchip/rk3568/drivers/otp/
H A Dotp.c39 reg = mmio_read_32(CRU_BASE + CRU_CLKGATES_CON(26)); in enable_otp_clk()
41 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(26), in enable_otp_clk()
46 reg = mmio_read_32(CRU_BASE + CRU_CLKGATES_CON(26)); in enable_otp_clk()
48 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(26), in enable_otp_clk()
53 reg = mmio_read_32(CRU_BASE + CRU_CLKGATES_CON(26)); in enable_otp_clk()
55 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(26), in enable_otp_clk()
60 reg = mmio_read_32(CRU_BASE + CRU_CLKGATES_CON(34)); in enable_otp_clk()
62 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(34), in enable_otp_clk()
99 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(26), in restore_otp_clk()
104 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(26), in restore_otp_clk()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3288/drivers/secure/
H A Dsecure.c147 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1), in secure_sgrf_init()
150 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4), in secure_sgrf_init()
156 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1), (RST_DMA1_MSK << 16)); in secure_sgrf_init()
158 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4), (RST_DMA2_MSK << 16)); in secure_sgrf_init()
/rk3399_ARM-atf/plat/rockchip/rk3568/drivers/soc/
H A Dsoc.c64 mmio_write_32(CRU_BASE + CRU_MODE_CON00, 0x03 << (16 + clk_pll * 2)); in set_pll_slow_mode()
78 mmio_write_32(CRU_BASE + CRU_GLB_SRST_FST, GLB_SRST_FST_CFG_VAL); in soc_global_soft_reset()
91 mmio_write_32(CRU_BASE + 0x00dc, 0x01030103); in rockchip_system_reset_init()
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/gpio/
H A Drk3399_gpio.c93 .clkgate_reg = CRU_BASE + CRU_CLKGATE_CON(31),
100 .clkgate_reg = CRU_BASE + CRU_CLKGATE_CON(31),
107 .clkgate_reg = CRU_BASE + CRU_CLKGATE_CON(31),
308 cru_gate_save = mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(31)); in plat_rockchip_save_gpio()
316 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in plat_rockchip_save_gpio()
338 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in plat_rockchip_save_gpio()
360 cru_gate_save = mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(31)); in plat_rockchip_restore_gpio()
368 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in plat_rockchip_restore_gpio()
384 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in plat_rockchip_restore_gpio()
/rk3399_ARM-atf/plat/rockchip/rk3576/scmi/
H A Drk3576_clk.c661 mode = mmio_read_32(CRU_BASE + CRU_MODE_CON) & in rk3576_bpll_get_rate()
667 m = (mmio_read_32(CRU_BASE + CRU_PLL_CON(0)) >> in rk3576_bpll_get_rate()
670 p = (mmio_read_32(CRU_BASE + CRU_PLL_CON(1)) >> in rk3576_bpll_get_rate()
673 s = (mmio_read_32(CRU_BASE + CRU_PLL_CON(1)) >> in rk3576_bpll_get_rate()
676 k = (mmio_read_32(CRU_BASE + CRU_PLL_CON(2)) >> in rk3576_bpll_get_rate()
823 if ((mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(165)) & 0x100) != 0) in clk_scmi_gpu_get_rate()
826 div = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(165)) & 0x1f; in clk_scmi_gpu_get_rate()
827 src = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(165)) & 0x00e0; in clk_scmi_gpu_get_rate()
873 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(165), in clk_gpu_set_rate()
875 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(165), in clk_gpu_set_rate()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/dram/
H A Dsuspend.c131 mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(4), in rkclk_ddr_reset()
486 mmio_clrsetbits_32(CRU_BASE + CRU_GLB_RST_CON, 0x3, 0x3); in dram_all_config()
655 mmio_write_32((CRU_BASE + CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); in pmusram_restore_pll()
657 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 0), src[0] | REG_SOC_WMSK); in pmusram_restore_pll()
658 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 1), src[1] | REG_SOC_WMSK); in pmusram_restore_pll()
659 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 2), src[2]); in pmusram_restore_pll()
660 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 4), src[4] | REG_SOC_WMSK); in pmusram_restore_pll()
661 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 5), src[5] | REG_SOC_WMSK); in pmusram_restore_pll()
663 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), src[3] | REG_SOC_WMSK); in pmusram_restore_pll()
665 while ((mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, 2)) & in pmusram_restore_pll()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3368/
H A Drk3368_def.h22 #define CRU_BASE 0xff760000 macro
53 #define CRU_BASE 0xff760000 macro
/rk3399_ARM-atf/plat/rockchip/rk3368/drivers/ddr/
H A Dddr_rk3368.c390 p_ddr_reg->dpllmodeaddr = CRU_BASE + PLL_CONS(DPLL_ID, 3); in ddr_reg_save()
394 p_ddr_reg->dpllresetaddr = CRU_BASE + PLL_CONS(DPLL_ID, 3); in ddr_reg_save()
397 p_ddr_reg->dpllconaddr = CRU_BASE + PLL_CONS(DPLL_ID, 0); in ddr_reg_save()
400 p_ddr_reg->dpllcon[0] = (mmio_read_32(CRU_BASE + in ddr_reg_save()
404 p_ddr_reg->dpllcon[1] = (mmio_read_32(CRU_BASE + in ddr_reg_save()
407 p_ddr_reg->dpllcon[2] = (mmio_read_32(CRU_BASE + in ddr_reg_save()
410 p_ddr_reg->dpllcon[3] = (mmio_read_32(CRU_BASE + in ddr_reg_save()
419 p_ddr_reg->dplllockaddr = CRU_BASE + PLL_CONS(DPLL_ID, 1); in ddr_reg_save()
424 p_ddr_reg->ddrpllsrcdivaddr = CRU_BASE + CRU_CLKSELS_CON(13); in ddr_reg_save()
425 p_ddr_reg->ddrpllsrcdiv = (mmio_read_32(CRU_BASE + CRU_CLKSELS_CON(13)) in ddr_reg_save()
[all …]
/rk3399_ARM-atf/plat/rockchip/px30/drivers/pmu/
H A Dpmu.c528 mmio_write_32(CRU_BASE + (con), ((msk) << 16) | 0xffff)
530 mmio_write_32(CRU_BASE + (con), ((~(msk)) << 16) | 0xffff)
550 mmio_read_32(CRU_BASE + CRU_CLKGATES_CON(i)); in clk_gate_suspend()
551 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), in clk_gate_suspend()
572 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), in clk_gate_resume()
875 mmio_write_32(CRU_BASE + CRU_MODE, val); in pll_set_mode()
887 pll_base = CRU_BASE + CRU_PLL_CONS(pll_id, 0); in pll_suspend()
905 pll_base = CRU_BASE + CRU_PLL_CONS(pll_id, 0); in pll_resume()
921 ddr_data.cru_mode_save = mmio_read_32(CRU_BASE + CRU_MODE); in pm_plls_suspend()
923 ddr_data.clk_sel0 = mmio_read_32(CRU_BASE + CRU_CLKSELS_CON(0)); in pm_plls_suspend()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3328/drivers/soc/
H A Dsoc.c40 MAP_REGION_FLAT(CRU_BASE, CRU_SIZE,
146 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(3), DMA_SOFTRST_REQ); in sgrf_init()
148 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(3), DMA_SOFTRST_RLS); in sgrf_init()
/rk3399_ARM-atf/plat/rockchip/rk3288/drivers/pmu/
H A Dpmu.c133 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(0), in cpus_power_domain_on()
142 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(0), BIT(cpu_id) << 16); in cpus_power_domain_on()
158 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(0), in cpus_power_domain_off()
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/pmu/
H A Dplat_pmu_macros.S53 ldr x7, =(CRU_BASE + 0xc)
110 mov x5, CRU_BASE
H A Dpmu.c586 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), in clst_pwr_domain_suspend()
599 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), in clst_pwr_domain_suspend()
619 pll_st = mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, 3)) >> in clst_pwr_domain_resume()
843 clk_ddrc_save = mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(3)); in sys_slp_config()
844 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(3), WMSK_BIT(1)); in sys_slp_config()
929 gpio_2_4_clk_gate = (mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(31)) >> in suspend_apio()
933 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in suspend_apio()
1053 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in resume_apio()
1283 store_cru[i / 4] = mmio_read_32(CRU_BASE + i); in cru_register_save()
1306 mmio_write_32(CRU_BASE + i, store_cru[i / 4]); in cru_register_restore()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3576/drivers/pmu/
H A Dpmu.c326 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), in clk_gate_con_disable()
329 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), in clk_gate_con_disable()
355 clk_save[j] = mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(i)); in clk_gate_con_save()
378 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), in clk_gate_con_restore()
893 ddr_data.cru_mode_con = mmio_read_32(CRU_BASE + 0x280); in pm_pll_suspend()
897 mmio_write_32(CRU_BASE + 0x280, 0x03ff0000); in pm_pll_suspend()
907 mmio_write_32(CRU_BASE + 0x280, WITH_16BITS_WMSK(ddr_data.cru_mode_con)); in pm_pll_restore()
974 mmio_write_32(CRU_BASE + CRU_MODE_CON, 0x003f0000); in rockchip_soc_soft_reset()
980 mmio_write_32(CRU_BASE + CRU_GLB_SRST_FST, GLB_SRST_FST_CFG_VAL); in rockchip_soc_soft_reset()
/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/soc/
H A Dsoc.c70 mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, 0xffdf); in system_reset_init()
/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/scmi/
H A Drk3588_clk.c918 if ((mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(158)) & 0x4000) != 0) { in clk_scmi_gpu_get_rate()
921 div = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(158)) & 0x1f; in clk_scmi_gpu_get_rate()
922 src = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(158)) & 0x00e0; in clk_scmi_gpu_get_rate()
975 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(158), in clk_gpu_set_rate()
982 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(158), in clk_gpu_set_rate()
985 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(158), in clk_gpu_set_rate()
987 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(158), in clk_gpu_set_rate()
1016 if ((mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(74)) & 0x1) != 0) { in clk_scmi_npu_get_rate()
1019 div = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(73)) & 0x007c; in clk_scmi_npu_get_rate()
1021 src = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(73)) & 0x0380; in clk_scmi_npu_get_rate()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3568/
H A Drk3568_def.h42 #define CRU_BASE 0xfdd20000 macro

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