Lines Matching refs:CRU_BASE
297 mmio_write_32(CRU_BASE + RK3568_CLK_SEL(0), in rk3568_apll_set_rate()
302 mmio_write_32(CRU_BASE + 0xc0, in rk3568_apll_set_rate()
307 mmio_write_32(CRU_BASE + RK3568_PLLCON(0), in rk3568_apll_set_rate()
311 mmio_write_32(CRU_BASE + RK3568_PLLCON(0), in rk3568_apll_set_rate()
315 mmio_write_32(CRU_BASE + RK3568_PLLCON(1), in rk3568_apll_set_rate()
319 mmio_write_32(CRU_BASE + RK3568_PLLCON(1), in rk3568_apll_set_rate()
323 mmio_write_32(CRU_BASE + RK3568_PLLCON(1), in rk3568_apll_set_rate()
330 if (mmio_read_32(CRU_BASE + RK3568_PLLCON(1)) & in rk3568_apll_set_rate()
340 mmio_write_32(CRU_BASE + 0xc0, in rk3568_apll_set_rate()
353 mode = (mmio_read_32(CRU_BASE + 0xc0) >> RK3568_PLL_MODE_SHIFT) & in rk3568_apll_get_rate()
359 fbdiv = (mmio_read_32(CRU_BASE + RK3568_PLLCON(0)) >> in rk3568_apll_get_rate()
362 postdiv1 = (mmio_read_32(CRU_BASE + RK3568_PLLCON(0)) >> in rk3568_apll_get_rate()
365 refdiv = (mmio_read_32(CRU_BASE + RK3568_PLLCON(1)) >> in rk3568_apll_get_rate()
368 postdiv2 = (mmio_read_32(CRU_BASE + RK3568_PLLCON(1)) >> in rk3568_apll_get_rate()
388 mmio_write_32(CRU_BASE + RK3568_CLK_SEL(0), in clk_cpu_set_rate()
390 mmio_write_32(CRU_BASE + RK3568_CLK_SEL(1), in clk_cpu_set_rate()
393 mmio_write_32(CRU_BASE + RK3568_CLK_SEL(3), in clk_cpu_set_rate()
396 mmio_write_32(CRU_BASE + RK3568_CLK_SEL(4), in clk_cpu_set_rate()
400 mmio_write_32(CRU_BASE + RK3568_CLK_SEL(2), CLKDIV_4BITS_SHF0(3)); in clk_cpu_set_rate()
403 mmio_write_32(CRU_BASE + RK3568_CLK_SEL(0), CPU_CLK_PATH_NOR_GPLL); in clk_cpu_set_rate()
405 mmio_write_32(CRU_BASE + RK3568_CLK_SEL(2), SCLK_PATH_NOR_GPLL); in clk_cpu_set_rate()
413 mmio_write_32(CRU_BASE + RK3568_CLK_SEL(0), CLK_CORE_PATH_DIR_APLL); in clk_cpu_set_rate()
418 mmio_write_32(CRU_BASE + RK3568_CLK_SEL(3), in clk_cpu_set_rate()
423 mmio_write_32(CRU_BASE + RK3568_CLK_SEL(4), in clk_cpu_set_rate()
428 mmio_write_32(CRU_BASE + RK3568_CLK_SEL(2), in clk_cpu_set_rate()
431 mmio_write_32(CRU_BASE + RK3568_CLK_SEL(2), in clk_cpu_set_rate()
435 mmio_write_32(CRU_BASE + RK3568_CLK_SEL(2), in clk_cpu_set_rate()
438 mmio_write_32(CRU_BASE + RK3568_CLK_SEL(2), in clk_cpu_set_rate()
443 mmio_write_32(CRU_BASE + RK3568_CLK_SEL(0), in clk_cpu_set_rate()
445 mmio_write_32(CRU_BASE + RK3568_CLK_SEL(1), in clk_cpu_set_rate()
476 if (mmio_read_32(CRU_BASE + RK3568_CLK_SEL(6)) & 0x0800) { in clk_scmi_gpu_get_rate()
479 div = mmio_read_32(CRU_BASE + RK3568_CLK_SEL(6)); in clk_scmi_gpu_get_rate()
494 mmio_write_32(CRU_BASE + RK3568_CLK_SEL(6), CLKDIV_4BITS_SHF0(5)); in clk_gpu_set_rate()
496 mmio_write_32(CRU_BASE + RK3568_CLK_SEL(6), GPU_CLK_PATH_NOR_GPLL); in clk_gpu_set_rate()
510 mmio_write_32(CRU_BASE + RK3568_CLK_SEL(6), in clk_gpu_set_rate()
516 mmio_write_32(CRU_BASE + RK3568_CLK_SEL(6), CLKDIV_4BITS_SHF0((div - 1))); in clk_gpu_set_rate()
541 if (mmio_read_32(CRU_BASE + RK3568_CLK_SEL(7)) & 0x8000) { in clk_scmi_npu_get_rate()
544 div = mmio_read_32(CRU_BASE + RK3568_CLK_SEL(7)); in clk_scmi_npu_get_rate()
559 mmio_write_32(CRU_BASE + RK3568_CLK_SEL(7), in clk_npu_set_rate()
562 mmio_write_32(CRU_BASE + RK3568_CLK_SEL(7), in clk_npu_set_rate()
577 mmio_write_32(CRU_BASE + RK3568_CLK_SEL(7), in clk_npu_set_rate()
582 mmio_write_32(CRU_BASE + RK3568_CLK_SEL(7), in clk_npu_set_rate()