Merge changes I1bfa797e,I0ec7a70e into integration

* changes:
fix(tree): correct some typos
fix(rockchip): use semicolon instead of comma

fix(tree): correct some typos

found using codespell (https://github.com/codespell-project/codespell).

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6

fix(tree): correct some typos

found using codespell (https://github.com/codespell-project/codespell).

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373

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Merge "plat/rockchip: enable power domains of rk3399 before reset" into integration

plat/rockchip: enable power domains of rk3399 before reset

This patch fixes hangs that happen after soft resetting of rk3399.

Signed-off-by: Piotr Szczepanik <piter75@gmail.com>
Change-Id: If41b12b

plat/rockchip: enable power domains of rk3399 before reset

This patch fixes hangs that happen after soft resetting of rk3399.

Signed-off-by: Piotr Szczepanik <piter75@gmail.com>
Change-Id: If41b12ba1dfcb2ba937361b58eafd50bf5c483d4

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Merge pull request #1726 from antonio-nino-diaz-arm/an/includes

Sanitise includes across codebase

Sanitise includes across codebase

Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- inclu

Sanitise includes across codebase

Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}

The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).

For example, this patch had to be created because two headers were
called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a282 ("drivers: add tzc380 support").

This problem was introduced in commit 4ecca33988b9 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.

Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.

Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Merge pull request #1384 from rockchip-linux/for_m0_patch

for rk3399 suspend/resume

rockchip/rk3399: Add watchdog support in pmusram

To catch early hangs in resume, this sets up the watchdog before
anything else in the pmusram code (ignoring setting up the stack...).
This uses hard

rockchip/rk3399: Add watchdog support in pmusram

To catch early hangs in resume, this sets up the watchdog before
anything else in the pmusram code (ignoring setting up the stack...).
This uses hard coded settings for the watchdog until the proper
watchdog restore later on in the firmware/kernel.

This also restores the old watchdog register values before the PLLs
are restored to make sure we don't temporarily switch over to a 1/3s
timeout on the watchdog when the pclk_wdt goes from 4MHz to 100MHz.

Change-Id: I8f7652089a88783271b17482117b4609330abe80
Signed-off-by: Derek Basehore <dbasehore@chromium.org>

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Merge pull request #1070 from rockchip-linux/rk3399-fixes-logic

rockchip/rk3399: Support Turning off VD_LOGIC during suspend-to-ram

rockchip/rk3399: disable more powerdomain prepare for shutdown logic rail

Change-Id: Ia59adf48cf14eb627721264765bce50cb31065ef
Signed-off-by: Lin Huang <hl@rock-chips.com>

rockchip/rk3399: set ddr clock source back to dpll when ddr resume

when logic power rail shutdown, CRU register will back to reset
value, ddr use abpll as clock source when do suspend, we need to sa

rockchip/rk3399: set ddr clock source back to dpll when ddr resume

when logic power rail shutdown, CRU register will back to reset
value, ddr use abpll as clock source when do suspend, we need to save
and dpll value in pmusram, then set back these ddr clock back to dpll
when dddr resume.

Change-Id: I95dc0173649e8515859cfa46b40a606e0cc2fe3f
Signed-off-by: Lin Huang <hl@rock-chips.com>

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Merge pull request #1029 from islmit01/im/fix_includes

Fix order of includes

Fix order of remaining platform #includes

This fix modifies the order of system includes to meet the ARM TF coding
standard. There are some exceptions to this change in order to retain
header groupi

Fix order of remaining platform #includes

This fix modifies the order of system includes to meet the ARM TF coding
standard. There are some exceptions to this change in order to retain
header groupings and where there are headers within #if statements.

Change-Id: Ib5b668c992d817cc860e97b29e16ef106d17e404
Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>

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Merge pull request #925 from dp-arm/dp/spdx

Use SPDX license identifiers

Use SPDX license identifiers

To make software license auditing simpler, use SPDX[0] license
identifiers instead of duplicating the license text in every file.

NOTE: Files that have been imported by

Use SPDX license identifiers

To make software license auditing simpler, use SPDX[0] license
identifiers instead of duplicating the license text in every file.

NOTE: Files that have been imported by FreeBSD have not been modified.

[0]: https://spdx.org/

Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>

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Merge pull request #835 from rockchip-linux/rk3399-atf-cleanup-20170210

RK3399 ARM TF clean up 20170210

rockchip: rk3399: Clean up and seprate secure parts from SoC codes

The goal is that make clear the secure and SoC codes. Now cleaning them
will help secure code extensions for RK3399 in the future.

rockchip: rk3399: Clean up and seprate secure parts from SoC codes

The goal is that make clear the secure and SoC codes. Now cleaning them
will help secure code extensions for RK3399 in the future.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

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rockchip: rk3399: configure the DDR secure region for BL31 image

Move the BL31 loaded base address 0x10000 to 0x1000, and configure
the the memory range 0~1MB is secure, the goal is that make sure
t

rockchip: rk3399: configure the DDR secure region for BL31 image

Move the BL31 loaded base address 0x10000 to 0x1000, and configure
the the memory range 0~1MB is secure, the goal is that make sure
the BL31 image will be not modified.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

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rockchip: Clean up header and referenced files

So far, there are more and more features are supported on the RK3399,
meanwhile, these features are increasingly being defined and intertwined.
It's ti

rockchip: Clean up header and referenced files

So far, there are more and more features are supported on the RK3399,
meanwhile, these features are increasingly being defined and intertwined.
It's time to clean up and make them clearer.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

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rk3399: dram: use PMU M0 to do ddr frequency scaling

We used dcf do ddr frequency scaling, but we just include a dcf
binary, it hard to maintain later, we have M0 compile flow in ATF,
and M0 can als

rk3399: dram: use PMU M0 to do ddr frequency scaling

We used dcf do ddr frequency scaling, but we just include a dcf
binary, it hard to maintain later, we have M0 compile flow in ATF,
and M0 can also work for ddr frequency scaling, so let's use it.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

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rockchip: rk3399: dram: remove dram_init and dts_timing_receive function

we can reuse the dram config from loader, so we can remove dram_init()
and dts_timing_receive() funciton in dram.c, add the d

rockchip: rk3399: dram: remove dram_init and dts_timing_receive function

we can reuse the dram config from loader, so we can remove dram_init()
and dts_timing_receive() funciton in dram.c, add the dram_set_odt_pd()
function to get the odt and auto power down parameter from kernel.

This also removes the dcf_code_init function to allow the system to
actually boot.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

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Merge pull request #752 from rockchip-linux/rk3399/fixes-s2r-1107

rk3399: fixes and updates for s2r

rockchip: remove no needed code for rk3399

We have do something for clocks gate.

Fox example as the below:
susped:
clk_gate_con_save();
clk_gate_con_disable();

resume:
clk_gate_con_restore();
--

rockchip: remove no needed code for rk3399

We have do something for clocks gate.

Fox example as the below:
susped:
clk_gate_con_save();
clk_gate_con_disable();

resume:
clk_gate_con_restore();
--

SO, add the plls_suspend_prepare() and plls_resume_finish() are not
necessary to S2R, that will save S2R time if remove them.

BRANCH=none
BUG=chrome-os-partner:58870,chrome-os-partner:55934
TEST=build kevin, two dogfooders with suspend_stress_test
passing 3000 cycles and still going on.

Change-Id: Icfbabc0b3ea8d2b5108d4f3de99a803b6d459669
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

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rockchip: disable watchdog during suspend

The CA53 and CM0 WDT clock gating in rk3399 SGRF, and ATF is in charge of
it because the kernel can't touch SGRF.

Basically the WDT didn't stop at suspend

rockchip: disable watchdog during suspend

The CA53 and CM0 WDT clock gating in rk3399 SGRF, and ATF is in charge of
it because the kernel can't touch SGRF.

Basically the WDT didn't stop at suspend time, it just switched from the
24M to the 32k clock. That meant that the WDT would fire if you slept for
long enough. In other word, the watchdog timer over count will increase to
750 (24*1000/32) times.
The RK3399 HW watchdog interval is 21 seconds. When machine enters the
suspend, the watchdog will reset the system after 35.7 (750/21) hours.

BUG=chrome-os-partner:59257
TEST=daisydog checked and set value, powerd_dbus_suspend to verify.

Change-Id: I88bb2a05b7d67d5ffd292f9d05d033ae9a6a3593
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

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Merge pull request #745 from rockchip-linux/support-rk3399-dram

Support rk3399 dram