661 	mode = mmio_read_32(CRU_BASE + CRU_MODE_CON) &  in rk3576_bpll_get_rate()
667 	m = (mmio_read_32(CRU_BASE + CRU_PLL_CON(0)) >>  in rk3576_bpll_get_rate()
670 	p = (mmio_read_32(CRU_BASE + CRU_PLL_CON(1)) >>  in rk3576_bpll_get_rate()
673 	s = (mmio_read_32(CRU_BASE + CRU_PLL_CON(1)) >>  in rk3576_bpll_get_rate()
676 	k = (mmio_read_32(CRU_BASE + CRU_PLL_CON(2)) >>  in rk3576_bpll_get_rate()
823 	if ((mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(165)) & 0x100) != 0)  in clk_scmi_gpu_get_rate()
826 	div = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(165)) & 0x1f;  in clk_scmi_gpu_get_rate()
827 	src = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(165)) & 0x00e0;  in clk_scmi_gpu_get_rate()
873 		mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(165),  in clk_gpu_set_rate()
875 		mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(165),  in clk_gpu_set_rate()
882 	mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(165),  in clk_gpu_set_rate()
885 	mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(165),  in clk_gpu_set_rate()
887 	mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(165),  in clk_gpu_set_rate()
922 	if ((mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(86)) & 0x8000) != 0)  in clk_scmi_npu_get_rate()
925 	div_src = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(86)) & 0x07c;  in clk_scmi_npu_get_rate()
927 	src = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(86)) & 0x0180;  in clk_scmi_npu_get_rate()
929 	div = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(86)) & 0x7c00;  in clk_scmi_npu_get_rate()
973 		mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(86),  in clk_npu_set_rate()
975 		mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(86),  in clk_npu_set_rate()
977 		mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(86),  in clk_npu_set_rate()
984 	mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(86),  in clk_npu_set_rate()
986 	mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(86),  in clk_npu_set_rate()
989 	mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(86),  in clk_npu_set_rate()
991 	mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(86),  in clk_npu_set_rate()