Lines Matching refs:CRU_BASE
195 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(CPLL_ID)); in rockchip_soc_soft_reset()
196 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(GPLL_ID)); in rockchip_soc_soft_reset()
197 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(NPLL_ID)); in rockchip_soc_soft_reset()
198 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(APLL_ID)); in rockchip_soc_soft_reset()
201 mmio_write_32(CRU_BASE + CRU_GLB_SRST_FST, CRU_GLB_SRST_FST_VALUE); in rockchip_soc_soft_reset()
255 mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(i)); in clks_gating_suspend()
256 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), in clks_gating_suspend()
266 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), in clks_gating_resume()
275 if (mmio_read_32(CRU_BASE + PLL_CONS(pll_id, 1)) & in pm_pll_wait_lock()
286 mmio_write_32(CRU_BASE + PLL_CONS(pll_id, 1), in pll_pwr_dwn()
289 mmio_write_32(CRU_BASE + PLL_CONS(pll_id, 1), in pll_pwr_dwn()
292 mmio_write_32(CRU_BASE + PLL_CONS(pll_id, 1), in pll_pwr_dwn()
301 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(DPLL_ID)); in dpll_suspend()
306 mmio_read_32(CRU_BASE + PLL_CONS(DPLL_ID, i)); in dpll_suspend()
307 mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1), in dpll_suspend()
309 mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1), in dpll_suspend()
317 mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1), in dpll_resume()
319 mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1), in dpll_resume()
321 mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1), in dpll_resume()
327 if (mmio_read_32(CRU_BASE + PLL_CONS(DPLL_ID, 1)) & in dpll_resume()
336 mmio_write_32(CRU_BASE + CRU_CRU_MODE, in dpll_resume()
345 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(pll_id)); in pll_suspend()
350 mmio_read_32(CRU_BASE + PLL_CONS(pll_id, i)); in pll_suspend()
358 mmio_write_32(CRU_BASE + PLL_CONS(pll_id, 1), in pll_resume()
364 mmio_write_32(CRU_BASE + CRU_CRU_MODE, in pll_resume()
370 ddr_data.cru_mode_save = mmio_read_32(CRU_BASE + CRU_CRU_MODE); in pm_plls_suspend()
371 ddr_data.clk_sel0 = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(0)); in pm_plls_suspend()
372 ddr_data.clk_sel1 = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(1)); in pm_plls_suspend()
373 ddr_data.clk_sel18 = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(18)); in pm_plls_suspend()
374 ddr_data.clk_sel20 = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(20)); in pm_plls_suspend()
375 ddr_data.clk_sel24 = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(24)); in pm_plls_suspend()
376 ddr_data.clk_sel38 = mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(38)); in pm_plls_suspend()
383 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(0), in pm_plls_suspend()
387 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(1), in pm_plls_suspend()
391 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(20), in pm_plls_suspend()
395 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(24), in pm_plls_suspend()
399 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(18), in pm_plls_suspend()
403 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(38), in pm_plls_suspend()
411 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(38), in pm_plls_resume()
417 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(18), in pm_plls_resume()
421 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(24), in pm_plls_resume()
425 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(20), in pm_plls_resume()
429 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(1), in pm_plls_resume()
433 mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(0), in pm_plls_resume()
517 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(0), in ddr_suspend()
519 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(7), in ddr_suspend()
521 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(18), in ddr_suspend()
523 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(27), in ddr_suspend()
534 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(0), in dmc_restore()
536 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(7), in dmc_restore()
538 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(18), in dmc_restore()
540 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(27), in dmc_restore()
561 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(16), 0x20002000); in sram_dbg_uart_suspend()
562 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(2), 0x00040004); in sram_dbg_uart_suspend()
568 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(16), 0x20000000); in sram_dbg_uart_resume()
569 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(2), 0x00040000); in sram_dbg_uart_resume()