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Searched refs:BIT (Results 1 – 25 of 225) sorted by relevance

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/optee_os/core/include/drivers/
H A Dstm32mp13_rcc.h214 #define RCC_SECCFGR_HSISEC BIT(0)
215 #define RCC_SECCFGR_CSISEC BIT(1)
216 #define RCC_SECCFGR_HSESEC BIT(2)
217 #define RCC_SECCFGR_LSISEC BIT(3)
218 #define RCC_SECCFGR_LSESEC BIT(4)
219 #define RCC_SECCFGR_PLL12SEC BIT(8)
220 #define RCC_SECCFGR_PLL3SEC BIT(9)
221 #define RCC_SECCFGR_PLL4SEC BIT(10)
222 #define RCC_SECCFGR_MPUSEC BIT(11)
223 #define RCC_SECCFGR_AXISEC BIT(12)
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H A Dstm32mp25_rcc.h717 #define RCC_GRSTCSETR_SYSRST BIT(0)
720 #define RCC_C1RSTCSETR_C1RST BIT(0)
723 #define RCC_C1P1RSTCSETR_C1P1PORRST BIT(0)
724 #define RCC_C1P1RSTCSETR_C1P1RST BIT(1)
727 #define RCC_C2RSTCSETR_C2RST BIT(0)
730 #define RCC_CxRSTCSETR_CxRST BIT(0)
733 #define RCC_HWRSTSCLRR_PORRSTF BIT(0)
734 #define RCC_HWRSTSCLRR_BORRSTF BIT(1)
735 #define RCC_HWRSTSCLRR_PADRSTF BIT(2)
736 #define RCC_HWRSTSCLRR_HCSSRSTF BIT(3)
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H A Dstm32mp21_rcc.h656 #define RCC_GRSTCSETR_SYSRST BIT(0)
659 #define RCC_C1RSTCSETR_C1RST BIT(0)
662 #define RCC_C2RSTCSETR_C2RST BIT(0)
665 #define RCC_HWRSTSCLRR_PORRSTF BIT(0)
666 #define RCC_HWRSTSCLRR_BORRSTF BIT(1)
667 #define RCC_HWRSTSCLRR_PADRSTF BIT(2)
668 #define RCC_HWRSTSCLRR_HCSSRSTF BIT(3)
669 #define RCC_HWRSTSCLRR_VCORERSTF BIT(4)
670 #define RCC_HWRSTSCLRR_SYSC1RSTF BIT(5)
671 #define RCC_HWRSTSCLRR_SYSC2RSTF BIT(6)
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H A Dstm32mp1_rcc.h241 #define RCC_TZCR_TZEN BIT(0)
242 #define RCC_TZCR_MCKPROT BIT(1)
247 #define RCC_SELR_SRCRDY BIT(31)
273 #define RCC_DIVR_DIVRDY BIT(31)
282 #define RCC_TIMGXPRER_TIMGXPRE BIT(0)
291 #define RCC_BDCR_LSEON BIT(0)
292 #define RCC_BDCR_LSEBYP BIT(1)
293 #define RCC_BDCR_LSERDY BIT(2)
294 #define RCC_BDCR_DIGBYP BIT(3)
297 #define RCC_BDCR_LSECSSON BIT(8)
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H A Dimx_wdog.h35 #define WDT_WCR_WDA BIT(5)
36 #define WDT_WCR_SRS BIT(4)
37 #define WDT_WCR_WRE BIT(3)
38 #define WDT_WCR_WDE BIT(2)
39 #define WDT_WCR_WDZST BIT(0)
58 #define WDOG_CS_CMD32EN BIT(13)
59 #define WDOG_CS_ULK BIT(11)
60 #define WDOG_CS_RCS BIT(10)
61 #define WDOG_CS_EN BIT(7)
62 #define WDOG_CS_UPDATE BIT(5)
H A Dzynqmp_efuse.h44 #define ZYNQMP_EFUSE_MISC_USER_CTRL_USR_WRLK_0 BIT(0)
45 #define ZYNQMP_EFUSE_MISC_USER_CTRL_USR_WRLK_1 BIT(1)
46 #define ZYNQMP_EFUSE_MISC_USER_CTRL_USR_WRLK_2 BIT(2)
47 #define ZYNQMP_EFUSE_MISC_USER_CTRL_USR_WRLK_3 BIT(3)
48 #define ZYNQMP_EFUSE_MISC_USER_CTRL_USR_WRLK_4 BIT(4)
49 #define ZYNQMP_EFUSE_MISC_USER_CTRL_USR_WRLK_5 BIT(5)
50 #define ZYNQMP_EFUSE_MISC_USER_CTRL_USR_WRLK_6 BIT(6)
51 #define ZYNQMP_EFUSE_MISC_USER_CTRL_USR_WRLK_7 BIT(7)
H A Dstpmic1.h92 #define LDO_BUCK_ENABLE_MASK BIT(LDO_BUCK_ENABLE_POS)
94 #define LDO_BUCK_RANK_MASK BIT(0)
95 #define LDO_BUCK_RESET_MASK BIT(0)
121 #define ICC_EVENT_ENABLED BIT(4)
122 #define PWRCTRL_POLARITY_HIGH BIT(3)
123 #define PWRCTRL_PIN_VALID BIT(2)
124 #define RESTART_REQUEST_ENABLED BIT(1)
125 #define SOFTWARE_SWITCH_OFF_ENABLED BIT(0)
128 #define WAKEUP_DETECTOR_DISABLED BIT(4)
129 #define PWRCTRL_PD_ACTIVE BIT(3)
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H A Dls_dspi.h31 #define SPI_CPHA BIT(0) /* clock phase */
32 #define SPI_CPOL BIT(1) /* clock polarity */
33 #define SPI_CS_HIGH BIT(2) /* CS active high */
34 #define SPI_LSB_FIRST BIT(3) /* per-word bits-on-wire */
35 #define SPI_CONT BIT(4) /* Continuous CS mode */
/optee_os/core/drivers/clk/sam/
H A Dat91_pmc.h22 #define AT91_PMC_PCK BIT(0)
23 #define AT91RM9200_PMC_UDP BIT(1)
24 #define AT91RM9200_PMC_MCKUDP BIT(2)
25 #define AT91RM9200_PMC_UHP BIT(4)
26 #define AT91SAM926x_PMC_UHP BIT(6)
27 #define AT91SAM926x_PMC_UDP BIT(7)
28 #define AT91_PMC_PCK0 BIT(8)
29 #define AT91_PMC_PCK1 BIT(9)
30 #define AT91_PMC_PCK2 BIT(10)
31 #define AT91_PMC_PCK3 BIT(11)
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/optee_os/core/arch/arm/plat-rzn1/
H A Drzn1_tz.h17 #define TZ_INIT_CSB_SEC BIT(7) /* CoreSight AHB */
18 #define TZ_INIT_CSA_SEC BIT(6) /* CoreSight AXI */
19 #define TZ_INIT_YS_SEC BIT(5) /* Cortex-M3 System Bus interface */
20 #define TZ_INIT_YC_SEC BIT(4) /* Cortex-M3 ICode interface */
21 #define TZ_INIT_YD_SEC BIT(3) /* Cortex-M3 DCode interface */
22 #define TZ_INIT_Z_SEC BIT(2) /* Packet Engine */
23 #define TZ_INIT_I_SEC BIT(1) /* Peripheral Group */
24 #define TZ_INIT_F_SEC BIT(0) /* Peripheral Group */
27 #define TZ_TARG_W_SEC BIT(14) /* RTC */
28 #define TZ_TARG_PC_SEC BIT(9) /* DDR2/3 Controller */
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/optee_os/core/include/drivers/sam/
H A Dsama7-ddr.h17 #define DDR3PHY_PIR_DLLBYP BIT(17) /* DLL Bypass */
18 #define DDR3PHY_PIR_ITMSRST BIT(4) /* Interface Timing Module Soft Reset */
19 #define DDR3PHY_PIR_DLLLOCK BIT(2) /* DLL Lock */
20 #define DDR3PHY_PIR_DLLSRST BIT(1) /* DLL Soft Rest */
21 #define DDR3PHY_PIR_INIT BIT(0) /* Initialization Trigger */
25 #define DDR3PHY_PGCR_CKDV1 BIT(13) /* CK# Disable Value */
26 #define DDR3PHY_PGCR_CKDV0 BIT(12) /* CK Disable Value */
30 #define DDR3PHY_PGSR_IDONE BIT(0) /* Initialization Done */
34 #define DDR3PHY_ACDLLCR_DLLSRST BIT(30) /* DLL Soft Reset */
38 #define DDR3PHY_ACIOCR_CSPDD_CS0 BIT(18) /* CS#[0] Power Down Driver */
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H A Dat91_ddr.h34 #define AT91_DDRSDRC_NC_SDR9 BIT(0)
38 #define AT91_DDRSDRC_NC_DDR10 BIT(0)
44 #define AT91_DDRSDRC_NR_12 BIT(2)
53 #define AT91_DDRSDRC_RST_DLL BIT(7)
55 #define AT91_DDRSDRC_DICDS BIT(8)
57 #define AT91_DDRSDRC_DIS_DLL BIT(9)
59 #define AT91_DDRSDRC_OCD BIT(12)
61 #define AT91_DDRSDRC_DQMS BIT(16)
63 #define AT91_DDRSDRC_ACTBST BIT(18)
117 #define AT91_DDRSDRC_CLKFR BIT(2)
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/optee_os/core/arch/arm/plat-stm32mp2/
H A Dstm32_sysconf.h31 #define VDERAMCR_VDERAM_EN BIT(0)
32 #define VDERAMCR_MASK BIT(0)
46 #define CA35SS_SSC_CHGCLKREQ_ARM_CHGCLKREQ BIT(0)
47 #define CA35SS_SSC_CHGCLKREQ_ARM_CHGCLKREQ_MASK BIT(0)
49 #define CA35SS_SSC_CHGCLKREQ_ARM_CHGCLKACK_MASK BIT(1)
52 #define CA35SS_SSC_CHGCLKREQ_ARM_DIVSEL BIT(16)
53 #define CA35SS_SSC_CHGCLKREQ_ARM_DIVSELACK BIT(17)
81 #define CA35SS_SSC_PLL_EN_PLL_EN BIT(0)
83 #define CA35SS_SSC_PLL_EN_LOCKP_MASK BIT(1)
85 #define CA35SS_SSC_PLL_EN_NRESET_SWPLL BIT(2)
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/optee_os/core/include/mm/
H A Dtee_mmu_types.h14 #define TEE_MATTR_VALID_BLOCK BIT(0)
15 #define TEE_MATTR_TABLE BIT(3)
16 #define TEE_MATTR_PR BIT(4)
17 #define TEE_MATTR_PW BIT(5)
18 #define TEE_MATTR_PX BIT(6)
22 #define TEE_MATTR_UR BIT(7)
23 #define TEE_MATTR_UW BIT(8)
24 #define TEE_MATTR_UX BIT(9)
31 #define TEE_MATTR_GLOBAL BIT(10)
32 #define TEE_MATTR_SECURE BIT(11)
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/optee_os/core/include/dt-bindings/firewall/
H A Dstm32mp25-rif.h31 #define RIF_CID0_BF BIT(RIF_CID0)
32 #define RIF_CID1_BF BIT(RIF_CID1)
33 #define RIF_CID2_BF BIT(RIF_CID2)
34 #define RIF_CID3_BF BIT(RIF_CID3)
35 #define RIF_CID4_BF BIT(RIF_CID4)
36 #define RIF_CID5_BF BIT(RIF_CID5)
37 #define RIF_CID6_BF BIT(RIF_CID6)
38 #define RIF_CID7_BF BIT(RIF_CID7)
104 #define RIF_SEC_MASK BIT(16)
105 #define RIF_PRIV_MASK BIT(17)
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/optee_os/core/arch/arm/plat-stm32mp1/drivers/
H A Dstm32mp1_pwr.h22 #define PWR_CR1_MPU_RAM_LOW_SPEED BIT(9)
27 #define PWR_CR3_VDDSD1EN BIT(13)
28 #define PWR_CR3_VDDSD1RDY BIT(14)
29 #define PWR_CR3_VDDSD2EN BIT(15)
30 #define PWR_CR3_VDDSD2RDY BIT(16)
31 #define PWR_CR3_VDDSD1VALID BIT(22)
32 #define PWR_CR3_VDDSD2VALID BIT(23)
/optee_os/core/arch/arm/include/
H A Dffa.h108 #define FFA_NOTIF_FLAG_BITMAP_SP BIT(0)
109 #define FFA_NOTIF_FLAG_BITMAP_VM BIT(1)
110 #define FFA_NOTIF_FLAG_BITMAP_SPM BIT(2)
111 #define FFA_NOTIF_FLAG_BITMAP_HYP BIT(3)
114 #define FFA_NOTIF_INFO_GET_MORE_FLAG BIT(0)
127 #define FFA_MSG_FLAG_FRAMEWORK BIT(31)
141 #define FFA_PARTITION_INFO_GET_COUNT_FLAG BIT(0)
147 #define FFA_MEM_ACC_RW BIT(1)
150 #define FFA_MEM_ACC_EXE BIT(3)
156 #define FFA_MEMORY_REGION_FLAG_CLEAR BIT(0)
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H A Darm.h16 #define MIDR_PRIMARY_PART_NUM_MASK (BIT(MIDR_PRIMARY_PART_NUM_WIDTH) - 1)
20 #define MIDR_IMPLEMENTER_MASK (BIT(MIDR_IMPLEMENTER_WIDTH) - 1)
25 #define MIDR_VARIANT_MASK (BIT(MIDR_VARIANT_WIDTH) - 1)
29 #define MIDR_REVISION_MASK (BIT(MIDR_REVISION_WIDTH) - 1)
70 #define MPIDR_MT_MASK BIT(MPIDR_MT_SHIFT)
103 #define CTR_DMINLINE_MASK (BIT(4) - 1)
120 #define ARM32_CPSR_T BIT(5)
122 #define ARM32_CPSR_F BIT(6)
123 #define ARM32_CPSR_I BIT(7)
124 #define ARM32_CPSR_A BIT(8)
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/optee_os/core/drivers/
H A Dcdns_uart.c43 #define CDNS_UART_CONTROL_RXRES BIT(0)
44 #define CDNS_UART_CONTROL_TXRES BIT(1)
45 #define CDNS_UART_CONTROL_RXEN BIT(2)
46 #define CDNS_UART_CONTROL_TXEN BIT(4)
52 #define CDNS_UART_CHANNEL_STATUS_TFUL BIT(4)
53 #define CDNS_UART_CHANNEL_STATUS_TEMPTY BIT(3)
54 #define CDNS_UART_CHANNEL_STATUS_REMPTY BIT(1)
56 #define CDNS_UART_IRQ_RXTRIG BIT(0)
57 #define CDNS_UART_IRQ_RXTOUT BIT(8)
H A Dpl061_gpio.c55 if (data & BIT(offset)) in pl061_get_direction()
71 io_setbits8(base_addr + GPIODIR, BIT(offset)); in pl061_set_direction()
73 io_clrbits8(base_addr + GPIODIR, BIT(offset)); in pl061_set_direction()
94 if (io_read8(base_addr + BIT(offset + 2))) in pl061_get_value()
115 io_write8(base_addr + BIT(offset + 2), BIT(offset)); in pl061_set_value()
117 io_write8(base_addr + BIT(offset + 2), 0); in pl061_set_value()
132 if (data & BIT(offset)) in pl061_get_interrupt()
149 io_setbits8(base_addr + GPIOIE, BIT(offset)); in pl061_set_interrupt()
151 io_clrbits8(base_addr + GPIOIE, BIT(offset)); in pl061_set_interrupt()
198 if (data & BIT(offset)) in pl061_get_mode_control()
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H A Datmel_rtc.c25 #define RTC_CR_UPDCAL BIT(1)
26 #define RTC_CR_UPDTIM BIT(0)
29 #define RTC_MR_HR_MODE BIT(0)
30 #define RTC_MR_PERSIAN BIT(1)
31 #define RTC_MR_UTC BIT(2)
32 #define RTC_MR_NEGPPM BIT(4)
36 #define RTC_MR_HIGHPPM BIT(15)
42 #define RTC_SR_ACKUPD BIT(0)
43 #define RTC_SR_SEC BIT(2)
46 #define RTC_SCCR_ACKCLR BIT(0)
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/optee_os/lib/libutee/include/
H A Dpta_stm32mp_bsec.h83 #define PTA_BSEC_LOCK_PERM BIT(30)
84 #define PTA_BSEC_LOCK_SHADOW_R BIT(29)
85 #define PTA_BSEC_LOCK_SHADOW_W BIT(28)
86 #define PTA_BSEC_LOCK_SHADOW_P BIT(27)
87 #define PTA_BSEC_LOCK_ERROR BIT(26)
/optee_os/core/drivers/scmi-msg/
H A Dreset_domain.h19 #define SCMI_RESET_STATE_ARCH BIT(31)
51 #define SCMI_RESET_DOMAIN_ATTR_ASYNC BIT(31)
52 #define SCMI_RESET_DOMAIN_ATTR_NOTIF BIT(30)
77 #define SCMI_RESET_DOMAIN_ASYNC BIT(2)
78 #define SCMI_RESET_DOMAIN_EXPLICIT BIT(1)
79 #define SCMI_RESET_DOMAIN_AUTO BIT(0)
96 #define SCMI_RESET_DOMAIN_DO_NOTIFY BIT(0)
/optee_os/core/arch/arm/include/sm/
H A Doptee_smc.h301 #define OPTEE_SMC_NSEC_CAP_UNIPROCESSOR BIT(0)
303 #define OPTEE_SMC_SEC_CAP_HAVE_RESERVED_SHM BIT(0)
305 #define OPTEE_SMC_SEC_CAP_UNREGISTERED_SHM BIT(1)
310 #define OPTEE_SMC_SEC_CAP_DYNAMIC_SHM BIT(2)
312 #define OPTEE_SMC_SEC_CAP_VIRTUALIZATION BIT(3)
314 #define OPTEE_SMC_SEC_CAP_MEMREF_NULL BIT(4)
316 #define OPTEE_SMC_SEC_CAP_ASYNC_NOTIF BIT(5)
318 #define OPTEE_SMC_SEC_CAP_RPC_ARG BIT(6)
320 #define OPTEE_SMC_SEC_CAP_RPMB_PROBE BIT(7)
322 #define OPTEE_SMC_SEC_CAP_PROTMEM BIT(8)
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/optee_os/ldelf/include/
H A Dldelf.h44 #define DUMP_MAP_READ BIT(0)
45 #define DUMP_MAP_WRITE BIT(1)
46 #define DUMP_MAP_EXEC BIT(2)
47 #define DUMP_MAP_SECURE BIT(3)
48 #define DUMP_MAP_EPHEM BIT(4)
49 #define DUMP_MAP_LDELF BIT(7)

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