xref: /optee_os/core/arch/arm/plat-stm32mp1/drivers/stm32mp1_pwr.h (revision 155ebf230015659f32d01c1e67dc52daca5a1e94)
1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /*
3  * Copyright (c) 2018-2023, STMicroelectronics
4  */
5 
6 #ifndef __STM32MP1_PWR_H
7 #define __STM32MP1_PWR_H
8 
9 #include <drivers/regulator.h>
10 #include <types_ext.h>
11 #include <util.h>
12 
13 #define PWR_CR1_OFF		0x00
14 #define PWR_CR2_OFF		0x08
15 #define PWR_CR3_OFF		0x0c
16 #define PWR_MPUCR_OFF		0x10
17 #define PWR_WKUPCR_OFF		0x20
18 #define PWR_MPUWKUPENR_OFF	0x28
19 
20 #ifdef CFG_STM32MP13
21 /* CR1 register bitfield for STM32MP13 variants */
22 #define PWR_CR1_MPU_RAM_LOW_SPEED	BIT(9)
23 #define PWR_MPU_RAM_LOW_SPEED_THRESHOLD 1320000
24 #endif
25 
26 /* CR3 register bitfield for STM32MP13 variants */
27 #define PWR_CR3_VDDSD1EN	BIT(13)
28 #define PWR_CR3_VDDSD1RDY	BIT(14)
29 #define PWR_CR3_VDDSD2EN	BIT(15)
30 #define PWR_CR3_VDDSD2RDY	BIT(16)
31 #define PWR_CR3_VDDSD1VALID	BIT(22)
32 #define PWR_CR3_VDDSD2VALID	BIT(23)
33 
34 #define PWR_OFFSET_MASK		0x3fUL
35 
36 enum pwr_regulator {
37 	PWR_REG11 = 0,
38 	PWR_REG18,
39 	PWR_USB33,
40 	PWR_REGU_COUNT
41 };
42 
43 vaddr_t stm32_pwr_base(void);
44 
45 unsigned int stm32mp1_pwr_regulator_mv(enum pwr_regulator id);
46 void stm32mp1_pwr_regulator_set_state(enum pwr_regulator id, bool enable);
47 bool stm32mp1_pwr_regulator_is_enabled(enum pwr_regulator id);
48 
49 /* Returns the registered regulator related to @id or NULL */
50 struct regulator *stm32mp1_pwr_get_regulator(enum pwr_regulator id);
51 #endif /*__STM32MP1_PWR_H*/
52