Lines Matching refs:BIT
17 #define DDR3PHY_PIR_DLLBYP BIT(17) /* DLL Bypass */
18 #define DDR3PHY_PIR_ITMSRST BIT(4) /* Interface Timing Module Soft Reset */
19 #define DDR3PHY_PIR_DLLLOCK BIT(2) /* DLL Lock */
20 #define DDR3PHY_PIR_DLLSRST BIT(1) /* DLL Soft Rest */
21 #define DDR3PHY_PIR_INIT BIT(0) /* Initialization Trigger */
25 #define DDR3PHY_PGCR_CKDV1 BIT(13) /* CK# Disable Value */
26 #define DDR3PHY_PGCR_CKDV0 BIT(12) /* CK Disable Value */
30 #define DDR3PHY_PGSR_IDONE BIT(0) /* Initialization Done */
34 #define DDR3PHY_ACDLLCR_DLLSRST BIT(30) /* DLL Soft Reset */
38 #define DDR3PHY_ACIOCR_CSPDD_CS0 BIT(18) /* CS#[0] Power Down Driver */
39 #define DDR3PHY_ACIOCR_CKPDD_CK0 BIT(8) /* CK[0] Power Down Driver */
40 #define DDR3PHY_ACIORC_ACPDD BIT(3) /* AC Power Down Driver */
44 #define DDR3PHY_DXCCR_DXPDR BIT(3) /* Data Power Down Receiver */
48 #define DDR3PHY_DSGCR_ODTPDD_ODT0 BIT(20) /* ODT[0] Power Down Driver */
61 #define DDR3PHY_DXDLLCR_DLLDIS BIT(31) /* DLL Disable */
85 #define UDDRC_PWRCTL_SELFREF_EN BIT(0) /* Automatic self-refresh */
86 #define UDDRC_PWRCTL_SELFREF_SW BIT(5) /* Software self-refresh */
91 #define UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN BIT(0)
96 #define UDDRC_SWCTRL_SW_DONE BIT(0)
100 #define UDDRC_SWSTAT_SW_DONE_ACK BIT(0) /* Register programming done */