1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2024, STMicroelectronics 4 */ 5 6 #ifndef __STM32_SYSCONF_H__ 7 #define __STM32_SYSCONF_H__ 8 9 #include <stdbool.h> 10 #include <stdint.h> 11 #include <util.h> 12 13 /* syscon banks */ 14 enum syscon_banks { 15 SYSCON_SYSCFG, 16 SYSCON_CA35SS, 17 SYSCON_NB_BANKS 18 }; 19 20 #define SYSCON_ID(bank, offset) (((bank) << 16) | \ 21 ((offset) & GENMASK_32(15, 0))) 22 23 /* 24 * SYSCFG register offsets (base relative) 25 */ 26 #define SYSCFG_VDERAMCR SYSCON_ID(SYSCON_SYSCFG, 0x1800) 27 28 /* 29 * SYSCFG_VDERAMCR register fields 30 */ 31 #define VDERAMCR_VDERAM_EN BIT(0) 32 #define VDERAMCR_MASK BIT(0) 33 34 /* 35 * CA35SS register offsets (base relative) 36 * Standardized Status and Control registers (SSC) access modes. 37 */ 38 #define CA35SS_SSC_CHGCLKREQ SYSCON_ID(SYSCON_CA35SS, 0x0U) 39 #define CA35SS_SSC_PLL_FREQ1 SYSCON_ID(SYSCON_CA35SS, 0x80U) 40 #define CA35SS_SSC_PLL_FREQ2 SYSCON_ID(SYSCON_CA35SS, 0x90U) 41 #define CA35SS_SSC_PLL_EN SYSCON_ID(SYSCON_CA35SS, 0xA0U) 42 43 /* 44 * CA35SS_SSC_CHGCLKREQ register fields 45 */ 46 #define CA35SS_SSC_CHGCLKREQ_ARM_CHGCLKREQ BIT(0) 47 #define CA35SS_SSC_CHGCLKREQ_ARM_CHGCLKREQ_MASK BIT(0) 48 49 #define CA35SS_SSC_CHGCLKREQ_ARM_CHGCLKACK_MASK BIT(1) 50 #define CA35SS_SSC_CHGCLKREQ_ARM_CHGCLKACK_SHIFT U(1) 51 52 #define CA35SS_SSC_CHGCLKREQ_ARM_DIVSEL BIT(16) 53 #define CA35SS_SSC_CHGCLKREQ_ARM_DIVSELACK BIT(17) 54 55 /* 56 * CA35SS_SSC_PLL_FREQ1 register fields 57 */ 58 #define CA35SS_SSC_PLL_FREQ1_FBDIV_MASK GENMASK_32(11, 0) 59 #define CA35SS_SSC_PLL_FREQ1_FBDIV_SHIFT U(0) 60 61 #define CA35SS_SSC_PLL_FREQ1_REFDIV_MASK GENMASK_32(21, 16) 62 #define CA35SS_SSC_PLL_FREQ1_REFDIV_SHIFT U(16) 63 64 #define CA35SS_SSC_PLL_FREQ1_MASK (CA35SS_SSC_PLL_FREQ1_REFDIV_MASK | \ 65 CA35SS_SSC_PLL_FREQ1_FBDIV_MASK) 66 67 /* 68 * CA35SS_SSC_PLL_FREQ2 register fields 69 */ 70 #define CA35SS_SSC_PLL_FREQ2_POSTDIV1_MASK GENMASK_32(2, 0) 71 #define CA35SS_SSC_PLL_FREQ2_POSTDIV1_SHIFT U(0) 72 73 #define CA35SS_SSC_PLL_FREQ2_POSTDIV2_MASK GENMASK_32(5, 3) 74 #define CA35SS_SSC_PLL_FREQ2_POSTDIV2_SHIFT U(3) 75 76 #define CA35SS_SSC_PLL_FREQ2_MASK GENMASK_32(5, 0) 77 78 /* 79 * CA35SS_SSC_PLL_EN register fields 80 */ 81 #define CA35SS_SSC_PLL_EN_PLL_EN BIT(0) 82 83 #define CA35SS_SSC_PLL_EN_LOCKP_MASK BIT(1) 84 85 #define CA35SS_SSC_PLL_EN_NRESET_SWPLL BIT(2) 86 #define CA35SS_SSC_PLL_EN_NRESET_SWPLL_MASK BIT(2) 87 88 /* 89 * CA35SS_SYSCFG registers 90 */ 91 #define CA35SS_SYSCFG_M33_ACCESS_CR SYSCON_ID(SYSCON_CA35SS, 0x2088U) 92 #define CA35SS_SYSCFG_M33_TZEN_CR SYSCON_ID(SYSCON_CA35SS, 0x20A0U) 93 #define CA35SS_SYSCFG_M33_INITSVTOR_CR SYSCON_ID(SYSCON_CA35SS, 0x20A4U) 94 #define CA35SS_SYSCFG_M33_INITNSVTOR_CR SYSCON_ID(SYSCON_CA35SS, 0x20A8U) 95 96 /* 97 * CA35SS_SYSCFG_M33_ACCESS_CR register offsets 98 */ 99 #define CA35SS_SYSCFG_M33_ACCESS_CR_SEC BIT(0) 100 #define CA35SS_SYSCFG_M33_ACCESS_CR_PRIV BIT(1) 101 102 /* 103 * CA35SS_SYSCFG_M33_TZEN_CR register offsets 104 */ 105 #define CA35SS_SYSCFG_M33_TZEN_CR_CFG_SECEXT BIT(0) 106 107 /* 108 * Write masked value is SYSCONF register 109 * @id: SYSCONF register ID, processed with SYSCON_ID() macro 110 * @value: Value to be written 111 * @bitmsk: Bit mask applied to @value 112 */ 113 void stm32mp_syscfg_write(uint32_t id, uint32_t value, uint32_t bitmsk); 114 115 /* 116 * Read SYSCONF reagister 117 * @id: SYSCONF register ID, processed with SYSCON_ID() macro 118 */ 119 uint32_t stm32mp_syscfg_read(uint32_t id); 120 121 /* 122 * Set safe reset state 123 * @status: True to enable safe reset, false to disable safe reset 124 */ 125 void stm32mp25_syscfg_set_safe_reset(bool status); 126 127 /* 128 * Manage OSPI address mapping 129 * @mm1_size: Size of memory addressed by the OSPI1 peripheral 130 * @mm2_size: Size of memory addressed by the OSPI2 peripheral 131 */ 132 void stm32mp25_syscfg_set_amcr(size_t mm1_size, size_t mm2_size); 133 134 #endif /*__STM32_SYSCONF_H__*/ 135