1*f1cf4b79SSumit Garg /* SPDX-License-Identifier: BSD-2-Clause */ 2*f1cf4b79SSumit Garg /* 3*f1cf4b79SSumit Garg * Copyright (c) 2017, Schneider Electric 4*f1cf4b79SSumit Garg * Copyright (c) 2020, Linaro Limited 5*f1cf4b79SSumit Garg */ 6*f1cf4b79SSumit Garg 7*f1cf4b79SSumit Garg #ifndef RZN1_TZ_H 8*f1cf4b79SSumit Garg #define RZN1_TZ_H 9*f1cf4b79SSumit Garg 10*f1cf4b79SSumit Garg #include <util.h> 11*f1cf4b79SSumit Garg 12*f1cf4b79SSumit Garg /* TZ config registers */ 13*f1cf4b79SSumit Garg #define FW_STATIC_TZA_INIT 0x4000C0D0 14*f1cf4b79SSumit Garg #define FW_STATIC_TZA_TARG 0x4000C0D4 15*f1cf4b79SSumit Garg 16*f1cf4b79SSumit Garg /* TZ initiatior ports */ 17*f1cf4b79SSumit Garg #define TZ_INIT_CSB_SEC BIT(7) /* CoreSight AHB */ 18*f1cf4b79SSumit Garg #define TZ_INIT_CSA_SEC BIT(6) /* CoreSight AXI */ 19*f1cf4b79SSumit Garg #define TZ_INIT_YS_SEC BIT(5) /* Cortex-M3 System Bus interface */ 20*f1cf4b79SSumit Garg #define TZ_INIT_YC_SEC BIT(4) /* Cortex-M3 ICode interface */ 21*f1cf4b79SSumit Garg #define TZ_INIT_YD_SEC BIT(3) /* Cortex-M3 DCode interface */ 22*f1cf4b79SSumit Garg #define TZ_INIT_Z_SEC BIT(2) /* Packet Engine */ 23*f1cf4b79SSumit Garg #define TZ_INIT_I_SEC BIT(1) /* Peripheral Group */ 24*f1cf4b79SSumit Garg #define TZ_INIT_F_SEC BIT(0) /* Peripheral Group */ 25*f1cf4b79SSumit Garg 26*f1cf4b79SSumit Garg /* TZ target ports */ 27*f1cf4b79SSumit Garg #define TZ_TARG_W_SEC BIT(14) /* RTC */ 28*f1cf4b79SSumit Garg #define TZ_TARG_PC_SEC BIT(9) /* DDR2/3 Controller */ 29*f1cf4b79SSumit Garg #define TZ_TARG_RA_SEC BIT(8) /* CoreSight */ 30*f1cf4b79SSumit Garg #define TZ_TARG_QB_SEC BIT(7) /* System Control */ 31*f1cf4b79SSumit Garg #define TZ_TARG_QA_SEC BIT(6) /* PG0 */ 32*f1cf4b79SSumit Garg #define TZ_TARG_NB_SEC BIT(5) /* Packet Engine */ 33*f1cf4b79SSumit Garg #define TZ_TARG_NA_SEC BIT(4) /* Public Key Processor */ 34*f1cf4b79SSumit Garg #define TZ_TARG_K_SEC BIT(3) /* Peripheral Group */ 35*f1cf4b79SSumit Garg #define TZ_TARG_J_SEC BIT(2) /* Peripheral Group */ 36*f1cf4b79SSumit Garg #define TZ_TARG_UB_SEC BIT(1) /* 2MB SRAM */ 37*f1cf4b79SSumit Garg #define TZ_TARG_UA_SEC BIT(0) /* 2MB SRAM */ 38*f1cf4b79SSumit Garg 39*f1cf4b79SSumit Garg #endif /* RZN1_TZ_H */ 40