Lines Matching refs:BIT

16 #define MIDR_PRIMARY_PART_NUM_MASK	(BIT(MIDR_PRIMARY_PART_NUM_WIDTH) - 1)
20 #define MIDR_IMPLEMENTER_MASK		(BIT(MIDR_IMPLEMENTER_WIDTH) - 1)
25 #define MIDR_VARIANT_MASK		(BIT(MIDR_VARIANT_WIDTH) - 1)
29 #define MIDR_REVISION_MASK		(BIT(MIDR_REVISION_WIDTH) - 1)
70 #define MPIDR_MT_MASK		BIT(MPIDR_MT_SHIFT)
103 #define CTR_DMINLINE_MASK	(BIT(4) - 1)
120 #define ARM32_CPSR_T		BIT(5)
122 #define ARM32_CPSR_F		BIT(6)
123 #define ARM32_CPSR_I		BIT(7)
124 #define ARM32_CPSR_A		BIT(8)
125 #define ARM32_CPSR_E		BIT(9)
132 #define CNTKCTL_PL0PCTEN	BIT(0) /* physical counter el0 access enable */
133 #define CNTKCTL_PL0VCTEN	BIT(1) /* virtual counter el0 access enable */