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Searched refs:set_parent (Results 1 – 25 of 130) sorted by relevance

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/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-composite.c29 return mux_ops->set_parent(mux_hw, index); in clk_composite_set_parent()
64 mux_hw && mux_ops && mux_ops->set_parent) { in clk_composite_determine_rate()
160 mux_ops->set_parent(mux_hw, index); in clk_composite_set_rate_and_parent()
162 mux_ops->set_parent(mux_hw, index); in clk_composite_set_rate_and_parent()
240 if (mux_ops->set_parent) in __clk_hw_register_composite()
241 clk_composite_ops->set_parent = clk_composite_set_parent; in __clk_hw_register_composite()
275 if (mux_ops->set_parent && rate_ops->set_rate) in __clk_hw_register_composite()
/OK3568_Linux_fs/kernel/drivers/clk/mediatek/
H A Dclk-mux.c134 .set_parent = mtk_clk_mux_set_parent_lock,
139 .set_parent = mtk_clk_mux_set_parent_setclr_lock,
147 .set_parent = mtk_clk_mux_set_parent_lock,
155 .set_parent = mtk_clk_mux_set_parent_setclr_lock,
/OK3568_Linux_fs/kernel/drivers/clk/tegra/
H A Dclk-tegra-super-cclk.c38 return tegra_clk_super_ops.set_parent(hw, index); in cclk_super_set_parent()
99 .set_parent = cclk_super_set_parent,
107 .set_parent = cclk_super_set_parent,
H A Dclk-periph.c33 return mux_ops->set_parent(mux_hw, index); in clk_periph_set_parent()
131 .set_parent = clk_periph_set_parent,
144 .set_parent = clk_periph_set_parent,
154 .set_parent = clk_periph_set_parent,
H A Dclk-super.c140 .set_parent = clk_super_set_parent,
193 .set_parent = clk_super_set_parent,
/OK3568_Linux_fs/kernel/drivers/clk/actions/
H A Dowl-composite.c147 .set_parent = owl_comp_set_parent,
164 .set_parent = owl_comp_set_parent,
193 .set_parent = owl_comp_set_parent,
H A Dowl-mux.c58 .set_parent = owl_mux_set_parent,
/OK3568_Linux_fs/kernel/drivers/clk/ti/
H A Ddpll.c38 .set_parent = &omap3_noncore_dpll_set_parent,
63 .set_parent = &omap3_noncore_dpll_set_parent,
76 .set_parent = &omap3_noncore_dpll_set_parent,
117 .set_parent = &omap3_noncore_dpll_set_parent,
129 .set_parent = &omap3_noncore_dpll_set_parent,
141 .set_parent = &omap3_noncore_dpll_set_parent,
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/regmap/
H A Dclk-regmap-composite.c56 return mux_ops->set_parent(mux_hw, index); in clk_regmap_composite_set_parent()
91 mux_hw && mux_ops && mux_ops->set_parent) { in clk_regmap_composite_determine_rate()
306 if (mux_ops->set_parent) in devm_clk_regmap_register_composite()
307 clk_composite_ops->set_parent = in devm_clk_regmap_register_composite()
/OK3568_Linux_fs/kernel/drivers/clk/qcom/
H A Dclk-rcg2.c372 .set_parent = clk_rcg2_set_parent,
383 .set_parent = clk_rcg2_set_parent,
510 .set_parent = clk_rcg2_set_parent,
568 .set_parent = clk_rcg2_set_parent,
638 .set_parent = clk_rcg2_set_parent,
729 .set_parent = clk_rcg2_set_parent,
816 .set_parent = clk_rcg2_set_parent,
954 .set_parent = clk_rcg2_set_parent,
1217 .set_parent = clk_rcg2_set_parent,
H A Dclk-rcg.c812 .set_parent = clk_rcg_set_parent,
823 .set_parent = clk_rcg_set_parent,
834 .set_parent = clk_rcg_set_parent,
846 .set_parent = clk_rcg_set_parent,
858 .set_parent = clk_rcg_set_parent,
870 .set_parent = clk_rcg_set_parent,
882 .set_parent = clk_dyn_rcg_set_parent,
H A Dclk-regmap-mux.c54 .set_parent = mux_set_parent,
H A Dkrait-cc.c43 ret = krait_mux_clk_ops.set_parent(&mux->hw, mux->safe_sel); in krait_notifier_cb()
52 ret = krait_mux_clk_ops.set_parent(&mux->hw, in krait_notifier_cb()
/OK3568_Linux_fs/kernel/drivers/clk/versatile/
H A Dclk-sp810.c67 .set_parent = clk_sp810_timerclken_set_parent,
128 init.ops->set_parent(&sp810->timerclken[i].hw, 1); in clk_sp810_of_setup()
/OK3568_Linux_fs/kernel/drivers/sh/clk/
H A Dcore.c523 if (clk->ops->set_parent) in clk_set_parent()
524 ret = clk->ops->set_parent(clk, parent); in clk_set_parent()
580 if (likely(clkp->ops->set_parent)) in clks_core_resume()
581 clkp->ops->set_parent(clkp, in clks_core_resume()
/OK3568_Linux_fs/kernel/drivers/clk/pxa/
H A Dclk-pxa.h24 .set_parent = dummy_clk_set_parent, \
75 .set_parent = name ## _set_parent, \
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/
H A Dclk-pll.c584 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3036_pll_set_params()
622 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3036_pll_set_params()
657 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3036_pll_enable()
668 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3036_pll_disable()
832 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3066_pll_set_params()
868 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3066_pll_set_params()
1097 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3399_pll_set_params()
1143 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3399_pll_set_params()
1381 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3588_pll_set_params()
1420 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3588_pll_set_params()
[all …]
/OK3568_Linux_fs/kernel/sound/soc/codecs/
H A Dtlv320aic32x4-clk.c271 .set_parent = clk_aic32x4_pll_set_parent,
295 .set_parent = clk_aic32x4_codec_clkin_set_parent,
382 .set_parent = clk_aic32x4_bdiv_set_parent,
/OK3568_Linux_fs/kernel/drivers/clk/imx/
H A Dclk-busy.c143 ret = busy->mux_ops->set_parent(&busy->mux.hw, index); in clk_busy_mux_set_parent()
152 .set_parent = clk_busy_mux_set_parent,
/OK3568_Linux_fs/kernel/drivers/clk/socfpga/
H A Dclk-gate.c168 .set_parent = socfpga_clk_set_parent,
235 ops->set_parent = NULL; in socfpga_gate_init()
/OK3568_Linux_fs/u-boot/include/
H A Dclk-uclass.h104 int (*set_parent)(struct clk *clk, struct clk *parent); member
/OK3568_Linux_fs/kernel/drivers/clk/sprd/
H A Dcomposite.c54 .set_parent = sprd_comp_set_parent,
H A Dmux.c73 .set_parent = sprd_mux_set_parent,
/OK3568_Linux_fs/kernel/drivers/clk/at91/
H A Dclk-i2s-mux.c47 .set_parent = clk_i2s_mux_set_parent,
/OK3568_Linux_fs/kernel/drivers/clk/sunxi-ng/
H A Dccu_mp.c242 .set_parent = ccu_mp_set_parent,
322 .set_parent = ccu_mp_set_parent,

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