1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2014, The Linux Foundation. All rights reserved.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/kernel.h>
7*4882a593Smuzhiyun #include <linux/bitops.h>
8*4882a593Smuzhiyun #include <linux/regmap.h>
9*4882a593Smuzhiyun #include <linux/export.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include "clk-regmap-mux.h"
12*4882a593Smuzhiyun
to_clk_regmap_mux(struct clk_hw * hw)13*4882a593Smuzhiyun static inline struct clk_regmap_mux *to_clk_regmap_mux(struct clk_hw *hw)
14*4882a593Smuzhiyun {
15*4882a593Smuzhiyun return container_of(to_clk_regmap(hw), struct clk_regmap_mux, clkr);
16*4882a593Smuzhiyun }
17*4882a593Smuzhiyun
mux_get_parent(struct clk_hw * hw)18*4882a593Smuzhiyun static u8 mux_get_parent(struct clk_hw *hw)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun struct clk_regmap_mux *mux = to_clk_regmap_mux(hw);
21*4882a593Smuzhiyun struct clk_regmap *clkr = to_clk_regmap(hw);
22*4882a593Smuzhiyun unsigned int mask = GENMASK(mux->width - 1, 0);
23*4882a593Smuzhiyun unsigned int val;
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun regmap_read(clkr->regmap, mux->reg, &val);
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun val >>= mux->shift;
28*4882a593Smuzhiyun val &= mask;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun if (mux->parent_map)
31*4882a593Smuzhiyun return qcom_find_cfg_index(hw, mux->parent_map, val);
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun return val;
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun
mux_set_parent(struct clk_hw * hw,u8 index)36*4882a593Smuzhiyun static int mux_set_parent(struct clk_hw *hw, u8 index)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun struct clk_regmap_mux *mux = to_clk_regmap_mux(hw);
39*4882a593Smuzhiyun struct clk_regmap *clkr = to_clk_regmap(hw);
40*4882a593Smuzhiyun unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift);
41*4882a593Smuzhiyun unsigned int val;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun if (mux->parent_map)
44*4882a593Smuzhiyun index = mux->parent_map[index].cfg;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun val = index;
47*4882a593Smuzhiyun val <<= mux->shift;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun return regmap_update_bits(clkr->regmap, mux->reg, mask, val);
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun const struct clk_ops clk_regmap_mux_closest_ops = {
53*4882a593Smuzhiyun .get_parent = mux_get_parent,
54*4882a593Smuzhiyun .set_parent = mux_set_parent,
55*4882a593Smuzhiyun .determine_rate = __clk_mux_determine_rate_closest,
56*4882a593Smuzhiyun };
57*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(clk_regmap_mux_closest_ops);
58