1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2018 Microchip Technology Inc,
4*4882a593Smuzhiyun * Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/clk-provider.h>
10*4882a593Smuzhiyun #include <linux/of.h>
11*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
12*4882a593Smuzhiyun #include <linux/regmap.h>
13*4882a593Smuzhiyun #include <linux/slab.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <soc/at91/atmel-sfr.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include "pmc.h"
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun struct clk_i2s_mux {
20*4882a593Smuzhiyun struct clk_hw hw;
21*4882a593Smuzhiyun struct regmap *regmap;
22*4882a593Smuzhiyun u8 bus_id;
23*4882a593Smuzhiyun };
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define to_clk_i2s_mux(hw) container_of(hw, struct clk_i2s_mux, hw)
26*4882a593Smuzhiyun
clk_i2s_mux_get_parent(struct clk_hw * hw)27*4882a593Smuzhiyun static u8 clk_i2s_mux_get_parent(struct clk_hw *hw)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun struct clk_i2s_mux *mux = to_clk_i2s_mux(hw);
30*4882a593Smuzhiyun u32 val;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun regmap_read(mux->regmap, AT91_SFR_I2SCLKSEL, &val);
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun return (val & BIT(mux->bus_id)) >> mux->bus_id;
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun
clk_i2s_mux_set_parent(struct clk_hw * hw,u8 index)37*4882a593Smuzhiyun static int clk_i2s_mux_set_parent(struct clk_hw *hw, u8 index)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun struct clk_i2s_mux *mux = to_clk_i2s_mux(hw);
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun return regmap_update_bits(mux->regmap, AT91_SFR_I2SCLKSEL,
42*4882a593Smuzhiyun BIT(mux->bus_id), index << mux->bus_id);
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun static const struct clk_ops clk_i2s_mux_ops = {
46*4882a593Smuzhiyun .get_parent = clk_i2s_mux_get_parent,
47*4882a593Smuzhiyun .set_parent = clk_i2s_mux_set_parent,
48*4882a593Smuzhiyun .determine_rate = __clk_mux_determine_rate,
49*4882a593Smuzhiyun };
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun struct clk_hw * __init
at91_clk_i2s_mux_register(struct regmap * regmap,const char * name,const char * const * parent_names,unsigned int num_parents,u8 bus_id)52*4882a593Smuzhiyun at91_clk_i2s_mux_register(struct regmap *regmap, const char *name,
53*4882a593Smuzhiyun const char * const *parent_names,
54*4882a593Smuzhiyun unsigned int num_parents, u8 bus_id)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun struct clk_init_data init = {};
57*4882a593Smuzhiyun struct clk_i2s_mux *i2s_ck;
58*4882a593Smuzhiyun int ret;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun i2s_ck = kzalloc(sizeof(*i2s_ck), GFP_KERNEL);
61*4882a593Smuzhiyun if (!i2s_ck)
62*4882a593Smuzhiyun return ERR_PTR(-ENOMEM);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun init.name = name;
65*4882a593Smuzhiyun init.ops = &clk_i2s_mux_ops;
66*4882a593Smuzhiyun init.parent_names = parent_names;
67*4882a593Smuzhiyun init.num_parents = num_parents;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun i2s_ck->hw.init = &init;
70*4882a593Smuzhiyun i2s_ck->bus_id = bus_id;
71*4882a593Smuzhiyun i2s_ck->regmap = regmap;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun ret = clk_hw_register(NULL, &i2s_ck->hw);
74*4882a593Smuzhiyun if (ret) {
75*4882a593Smuzhiyun kfree(i2s_ck);
76*4882a593Smuzhiyun return ERR_PTR(ret);
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun return &i2s_ck->hw;
80*4882a593Smuzhiyun }
81