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Searched refs:pll_div (Results 1 – 25 of 40) sorted by relevance

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/OK3568_Linux_fs/kernel/drivers/clk/x86/
H A Dclk-lgm.c122 static const struct clk_div_table pll_div[] = { variable
194 0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
196 4, PLL_DIV_WIDTH, 25, 1, 0, 0, pll_div),
198 8, PLL_DIV_WIDTH, 26, 1, 0, 0, pll_div),
200 12, PLL_DIV_WIDTH, 27, 1, 0, 0, pll_div),
203 pll_div),
205 0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
209 1, 0, 0, pll_div),
212 8, PLL_DIV_WIDTH, 26, 1, 0, 0, pll_div),
216 0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
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/OK3568_Linux_fs/kernel/sound/soc/codecs/
H A Dwm8804.c319 struct pll_div { struct
344 static int pll_factors(struct pll_div *pll_div, unsigned int target, in pll_factors() argument
359 pll_div->freqmode = post_table[i].freqmode; in pll_factors()
360 pll_div->mclkdiv = post_table[i].mclkdiv; in pll_factors()
372 pll_div->prescale = 0; in pll_factors()
376 pll_div->prescale = 1; in pll_factors()
385 pll_div->n = Ndiv; in pll_factors()
396 pll_div->k = K; in pll_factors()
417 struct pll_div pll_div; in wm8804_set_pll() local
419 ret = pll_factors(&pll_div, freq_out, freq_in, in wm8804_set_pll()
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H A Dwm9713.c753 struct _pll_div *pll_div, unsigned int source) in pll_factors() argument
764 pll_div->divsel = 1; in pll_factors()
768 pll_div->divctl = 1; in pll_factors()
770 pll_div->divctl = 0; in pll_factors()
773 pll_div->divsel = 0; in pll_factors()
774 pll_div->divctl = 0; in pll_factors()
781 pll_div->lf = 1; in pll_factors()
784 pll_div->lf = 0; in pll_factors()
792 pll_div->n = Ndiv; in pll_factors()
807 pll_div->k = K; in pll_factors()
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H A Dwm8580.c400 static int pll_factors(struct _pll_div *pll_div, unsigned int target, in pll_factors() argument
415 pll_div->freqmode = post_table[i].freqmode; in pll_factors()
416 pll_div->postscale = post_table[i].postscale; in pll_factors()
432 pll_div->prescale = 1; in pll_factors()
435 pll_div->prescale = 0; in pll_factors()
443 pll_div->n = Ndiv; in pll_factors()
451 pll_div->k = K; in pll_factors()
454 pll_div->n, pll_div->k, pll_div->prescale, pll_div->freqmode, in pll_factors()
455 pll_div->postscale); in pll_factors()
467 struct _pll_div pll_div; in wm8580_set_dai_pll() local
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H A Dwm8940.c519 static struct pll_ pll_div; variable
534 pll_div.pre_scale = 0; in pll_factors()
539 pll_div.pre_scale = 3; in pll_factors()
544 pll_div.pre_scale = 2; in pll_factors()
547 pll_div.pre_scale = 1; in pll_factors()
554 pll_div.n = Ndiv; in pll_factors()
569 pll_div.k = K; in pll_factors()
594 if (pll_div.k) in wm8940_set_dai_pll()
596 (pll_div.pre_scale << 4) | pll_div.n | (1 << 6)); in wm8940_set_dai_pll()
599 (pll_div.pre_scale << 4) | pll_div.n); in wm8940_set_dai_pll()
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H A Dwm8978.c409 struct wm8978_pll_div *pll_div, unsigned int target, unsigned int source) in pll_factors() argument
417 pll_div->div2 = 1; in pll_factors()
420 pll_div->div2 = 0; in pll_factors()
428 pll_div->n = n_div; in pll_factors()
436 pll_div->k = k; in pll_factors()
474 struct wm8978_pll_div pll_div; in wm8978_configure_pll() local
536 pll_factors(component, &pll_div, f2, wm8978->f_mclk); in wm8978_configure_pll()
539 __func__, pll_div.n, pll_div.k, pll_div.div2); in wm8978_configure_pll()
544 snd_soc_component_write(component, WM8978_PLL_N, (pll_div.div2 << 4) | pll_div.n); in wm8978_configure_pll()
545 snd_soc_component_write(component, WM8978_PLL_K1, pll_div.k >> 18); in wm8978_configure_pll()
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H A Dwm8974.c274 static void pll_factors(struct pll_ *pll_div, in pll_factors() argument
286 pll_div->pre_div = 1; in pll_factors()
289 pll_div->pre_div = 0; in pll_factors()
296 pll_div->n = Ndiv; in pll_factors()
311 pll_div->k = K; in pll_factors()
318 struct pll_ pll_div; in wm8974_set_dai_pll() local
332 pll_factors(&pll_div, freq_out, freq_in); in wm8974_set_dai_pll()
334 snd_soc_component_write(component, WM8974_PLLN, (pll_div.pre_div << 4) | pll_div.n); in wm8974_set_dai_pll()
335 snd_soc_component_write(component, WM8974_PLLK1, pll_div.k >> 18); in wm8974_set_dai_pll()
336 snd_soc_component_write(component, WM8974_PLLK2, (pll_div.k >> 9) & 0x1ff); in wm8974_set_dai_pll()
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H A Dwm8510.c271 static struct pll_ pll_div; variable
285 pll_div.pre_div = 1; in pll_factors()
288 pll_div.pre_div = 0; in pll_factors()
295 pll_div.n = Ndiv; in pll_factors()
310 pll_div.k = K; in pll_factors()
332 snd_soc_component_write(component, WM8510_PLLN, (pll_div.pre_div << 4) | pll_div.n); in wm8510_set_dai_pll()
333 snd_soc_component_write(component, WM8510_PLLK1, pll_div.k >> 18); in wm8510_set_dai_pll()
334 snd_soc_component_write(component, WM8510_PLLK2, (pll_div.k >> 9) & 0x1ff); in wm8510_set_dai_pll()
335 snd_soc_component_write(component, WM8510_PLLK3, pll_div.k & 0x1ff); in wm8510_set_dai_pll()
H A Dwm8983.c743 struct pll_div { struct
750 static int pll_factors(struct pll_div *pll_div, unsigned int target, in pll_factors() argument
756 pll_div->div2 = 0; in pll_factors()
760 pll_div->div2 = 1; in pll_factors()
769 pll_div->n = Ndiv; in pll_factors()
780 pll_div->k = K; in pll_factors()
790 struct pll_div pll_div; in wm8983_set_pll() local
799 ret = pll_factors(&pll_div, freq_out * 4 * 2, freq_in); in wm8983_set_pll()
809 (pll_div.div2 << WM8983_PLL_PRESCALE_SHIFT) in wm8983_set_pll()
810 | pll_div.n); in wm8983_set_pll()
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H A Dwm8985.c840 struct pll_div { struct
847 static int pll_factors(struct pll_div *pll_div, unsigned int target, in pll_factors() argument
853 pll_div->div2 = 0; in pll_factors()
857 pll_div->div2 = 1; in pll_factors()
866 pll_div->n = Ndiv; in pll_factors()
877 pll_div->k = K; in pll_factors()
888 struct pll_div pll_div; in wm8985_set_pll() local
896 ret = pll_factors(&pll_div, freq_out * 4 * 2, freq_in); in wm8985_set_pll()
902 (pll_div.div2 << WM8985_PLL_PRESCALE_SHIFT) in wm8985_set_pll()
903 | pll_div.n); in wm8985_set_pll()
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H A Dwm8960.c1141 struct _pll_div *pll_div) in pll_factors() argument
1154 pll_div->pre_div = 1; in pll_factors()
1157 pll_div->pre_div = 0; in pll_factors()
1164 pll_div->n = Ndiv; in pll_factors()
1179 pll_div->k = K; in pll_factors()
1182 pll_div->n, pll_div->k, pll_div->pre_div); in pll_factors()
1191 static struct _pll_div pll_div; in wm8960_set_pll() local
1195 ret = pll_factors(freq_in, freq_out, &pll_div); in wm8960_set_pll()
1209 reg |= pll_div.pre_div << 4; in wm8960_set_pll()
1210 reg |= pll_div.n; in wm8960_set_pll()
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H A Dwm8990.c806 static void pll_factors(struct _pll_div *pll_div, unsigned int target, in pll_factors() argument
816 pll_div->div2 = 1; in pll_factors()
819 pll_div->div2 = 0; in pll_factors()
825 pll_div->n = Ndiv; in pll_factors()
840 pll_div->k = K; in pll_factors()
847 struct _pll_div pll_div; in wm8990_set_dai_pll() local
850 pll_factors(&pll_div, freq_out * 4, freq_in); in wm8990_set_dai_pll()
861 snd_soc_component_write(component, WM8990_PLL1, pll_div.n | WM8990_SDM | in wm8990_set_dai_pll()
862 (pll_div.div2?WM8990_PRESCALE:0)); in wm8990_set_dai_pll()
863 snd_soc_component_write(component, WM8990_PLL2, (u8)(pll_div.k>>8)); in wm8990_set_dai_pll()
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H A Dwm8991.c877 static void pll_factors(struct _pll_div *pll_div, unsigned int target, in pll_factors() argument
887 pll_div->div2 = 1; in pll_factors()
890 pll_div->div2 = 0; in pll_factors()
896 pll_div->n = Ndiv; in pll_factors()
911 pll_div->k = K; in pll_factors()
919 struct _pll_div pll_div; in wm8991_set_dai_pll() local
922 pll_factors(&pll_div, freq_out * 4, freq_in); in wm8991_set_dai_pll()
934 snd_soc_component_write(component, WM8991_PLL1, pll_div.n | WM8991_SDM | in wm8991_set_dai_pll()
935 (pll_div.div2 ? WM8991_PRESCALE : 0)); in wm8991_set_dai_pll()
936 snd_soc_component_write(component, WM8991_PLL2, (u8)(pll_div.k>>8)); in wm8991_set_dai_pll()
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H A Dwm8753.c702 static void pll_factors(struct _pll_div *pll_div, unsigned int target, in pll_factors() argument
711 pll_div->div2 = 1; in pll_factors()
714 pll_div->div2 = 0; in pll_factors()
720 pll_div->n = Ndiv; in pll_factors()
735 pll_div->k = K; in pll_factors()
765 struct _pll_div pll_div; in wm8753_set_dai_pll() local
767 pll_factors(&pll_div, freq_out * 8, freq_in); in wm8753_set_dai_pll()
771 value = (pll_div.n << 5) + ((pll_div.k & 0x3c0000) >> 18); in wm8753_set_dai_pll()
775 value = (pll_div.k & 0x03fe00) >> 9; in wm8753_set_dai_pll()
779 value = pll_div.k & 0x0001ff; in wm8753_set_dai_pll()
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/OK3568_Linux_fs/u-boot/arch/arm/mach-davinci/
H A Dcpu.c116 static unsigned pll_div(volatile void *pllbase, unsigned offset) in pll_div() function
131 return pll_div(pllbase, PLLC_PREDIV); in pll_prediv()
133 return pll_div(pllbase, PLLC_PREDIV); in pll_prediv()
141 return pll_div(pllbase, PLLC_POSTDIV); in pll_postdiv()
144 return pll_div(pllbase, PLLC_POSTDIV); in pll_postdiv()
168 return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div)); in pll_sysclk_mhz()
/OK3568_Linux_fs/kernel/drivers/clk/imx/
H A Dclk-pll14xx.c122 u32 mdiv, pdiv, sdiv, pll_div; in clk_pll1416x_recalc_rate() local
125 pll_div = readl_relaxed(pll->base + 4); in clk_pll1416x_recalc_rate()
126 mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_recalc_rate()
127 pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT; in clk_pll1416x_recalc_rate()
128 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1416x_recalc_rate()
161 u32 pll_div) in clk_pll14xx_mp_change() argument
165 old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll14xx_mp_change()
166 old_pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT; in clk_pll14xx_mp_change()
/OK3568_Linux_fs/u-boot/drivers/clk/rockchip/
H A Dclk_rk3368.c31 struct pll_div { struct
48 static struct pll_div rk3368_pll_rates[] = { argument
113 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2);
114 static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2);
116 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2);
117 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6);
129 struct pll_div *rkclk_get_pll_config(ulong freq_hz) in rkclk_get_pll_config()
141 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div) in pll_para_config()
143 struct pll_div *best_div = NULL; in pll_para_config()
250 const struct pll_div *div) in rkclk_set_pll()
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H A Dclk_rk3399.c35 struct pll_div { struct
54 static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1); argument
56 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 3, 1);
57 static const struct pll_div npll_init_cfg = PLL_DIVISORS(NPLL_HZ, 1, 3, 1);
58 static const struct pll_div apll_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1);
59 static const struct pll_div apll_816_cfg = PLL_DIVISORS(816 * MHz, 1, 2, 1);
60 static const struct pll_div apll_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1);
62 static const struct pll_div *apll_cfgs[] = {
366 static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div) in rkclk_set_pll()
445 static int pll_para_config(u32 freq_hz, struct pll_div *div) in pll_para_config()
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H A Dclk_rk3066.c55 struct pll_div { struct
103 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
104 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
108 const struct pll_div *div, bool has_bwadj) in rkclk_set_pll()
144 static const struct pll_div dpll_cfg[] = { in rkclk_configure_ddr()
190 static const struct pll_div apll_cfg[] = { in rkclk_configure_cpu()
H A Dclk_rk3188.c56 struct pll_div { struct
101 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
102 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
106 const struct pll_div *div, bool has_bwadj) in rkclk_set_pll()
142 static const struct pll_div dpll_cfg[] = { in rkclk_configure_ddr()
188 static const struct pll_div apll_cfg[] = { in rkclk_configure_cpu()
/OK3568_Linux_fs/kernel/drivers/clk/meson/
H A Dvid-pll-div.c79 struct meson_vid_pll_div_data *pll_div = meson_vid_pll_div_data(clk); in meson_vid_pll_div_recalc_rate() local
82 div = _get_table_val(meson_parm_read(clk->map, &pll_div->val), in meson_vid_pll_div_recalc_rate()
83 meson_parm_read(clk->map, &pll_div->sel)); in meson_vid_pll_div_recalc_rate()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/display/
H A Dvlv_dsi_pll.c264 u32 pll_ctl, pll_div; in vlv_dsi_get_pclk() local
273 pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER); in vlv_dsi_get_pclk()
277 config->dsi_pll.div = pll_div; in vlv_dsi_get_pclk()
284 n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT; in vlv_dsi_get_pclk()
288 pll_div &= DSI_PLL_M1_DIV_MASK; in vlv_dsi_get_pclk()
289 pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT; in vlv_dsi_get_pclk()
303 if (lfsr_converts[i] == pll_div) in vlv_dsi_get_pclk()
/OK3568_Linux_fs/u-boot/arch/arm/mach-imx/mx7/
H A Dclock.c776 static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom, in enable_pll_video() argument
783 pll_div, pll_num, pll_denom); in enable_pll_video()
797 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | in enable_pll_video()
803 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | in enable_pll_video()
809 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | in enable_pll_video()
815 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | in enable_pll_video()
822 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | in enable_pll_video()
899 u32 pll_div, pll_num, pll_denom, post_div = 0; in mxs_set_lcdclk() local
943 pll_div = best / hck; in mxs_set_lcdclk()
945 pll_num = (best - hck * pll_div) * pll_denom / hck; in mxs_set_lcdclk()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-stm32f4.c720 struct stm32f4_pll_div *pll_div = to_pll_div_clk(div); in stm32f4_pll_div_set_rate() local
722 pll_state = stm32f4_pll_is_enabled(pll_div->hw_pll); in stm32f4_pll_div_set_rate()
725 stm32f4_pll_disable(pll_div->hw_pll); in stm32f4_pll_div_set_rate()
730 stm32f4_pll_enable(pll_div->hw_pll); in stm32f4_pll_div_set_rate()
747 struct stm32f4_pll_div *pll_div; in clk_register_pll_div() local
753 pll_div = kzalloc(sizeof(*pll_div), GFP_KERNEL); in clk_register_pll_div()
754 if (!pll_div) in clk_register_pll_div()
764 pll_div->div.reg = reg; in clk_register_pll_div()
765 pll_div->div.shift = shift; in clk_register_pll_div()
766 pll_div->div.width = width; in clk_register_pll_div()
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/OK3568_Linux_fs/u-boot/arch/arm/mach-imx/mx6/
H A Dclock.c552 static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom, in enable_pll_video() argument
559 pll_div, pll_num, pll_denom); in enable_pll_video()
571 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) | in enable_pll_video()
576 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) | in enable_pll_video()
581 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) | in enable_pll_video()
627 u32 pll_div, pll_num, pll_denom, post_div = 1; in mxs_set_lcdclk() local
698 pll_div = best / hck; in mxs_set_lcdclk()
700 pll_num = (best - hck * pll_div) * pll_denom / hck; in mxs_set_lcdclk()
711 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) in mxs_set_lcdclk()
748 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) in mxs_set_lcdclk()

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