1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * wm8940.c -- WM8940 ALSA Soc Audio driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Author: Jonathan Cameron <jic23@cam.ac.uk>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Based on wm8510.c
8*4882a593Smuzhiyun * Copyright 2006 Wolfson Microelectronics PLC.
9*4882a593Smuzhiyun * Author: Liam Girdwood <lrg@slimlogic.co.uk>
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * Not currently handled:
12*4882a593Smuzhiyun * Notch filter control
13*4882a593Smuzhiyun * AUXMode (inverting vs mixer)
14*4882a593Smuzhiyun * No means to obtain current gain if alc enabled.
15*4882a593Smuzhiyun * No use made of gpio
16*4882a593Smuzhiyun * Fast VMID discharge for power down
17*4882a593Smuzhiyun * Soft Start
18*4882a593Smuzhiyun * DLR and ALR Swaps not enabled
19*4882a593Smuzhiyun * Digital Sidetone not supported
20*4882a593Smuzhiyun */
21*4882a593Smuzhiyun #include <linux/module.h>
22*4882a593Smuzhiyun #include <linux/moduleparam.h>
23*4882a593Smuzhiyun #include <linux/kernel.h>
24*4882a593Smuzhiyun #include <linux/init.h>
25*4882a593Smuzhiyun #include <linux/delay.h>
26*4882a593Smuzhiyun #include <linux/pm.h>
27*4882a593Smuzhiyun #include <linux/i2c.h>
28*4882a593Smuzhiyun #include <linux/regmap.h>
29*4882a593Smuzhiyun #include <linux/slab.h>
30*4882a593Smuzhiyun #include <sound/core.h>
31*4882a593Smuzhiyun #include <sound/pcm.h>
32*4882a593Smuzhiyun #include <sound/pcm_params.h>
33*4882a593Smuzhiyun #include <sound/soc.h>
34*4882a593Smuzhiyun #include <sound/initval.h>
35*4882a593Smuzhiyun #include <sound/tlv.h>
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #include "wm8940.h"
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun struct wm8940_priv {
40*4882a593Smuzhiyun unsigned int sysclk;
41*4882a593Smuzhiyun struct regmap *regmap;
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun
wm8940_volatile_register(struct device * dev,unsigned int reg)44*4882a593Smuzhiyun static bool wm8940_volatile_register(struct device *dev, unsigned int reg)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun switch (reg) {
47*4882a593Smuzhiyun case WM8940_SOFTRESET:
48*4882a593Smuzhiyun return true;
49*4882a593Smuzhiyun default:
50*4882a593Smuzhiyun return false;
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
wm8940_readable_register(struct device * dev,unsigned int reg)54*4882a593Smuzhiyun static bool wm8940_readable_register(struct device *dev, unsigned int reg)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun switch (reg) {
57*4882a593Smuzhiyun case WM8940_SOFTRESET:
58*4882a593Smuzhiyun case WM8940_POWER1:
59*4882a593Smuzhiyun case WM8940_POWER2:
60*4882a593Smuzhiyun case WM8940_POWER3:
61*4882a593Smuzhiyun case WM8940_IFACE:
62*4882a593Smuzhiyun case WM8940_COMPANDINGCTL:
63*4882a593Smuzhiyun case WM8940_CLOCK:
64*4882a593Smuzhiyun case WM8940_ADDCNTRL:
65*4882a593Smuzhiyun case WM8940_GPIO:
66*4882a593Smuzhiyun case WM8940_CTLINT:
67*4882a593Smuzhiyun case WM8940_DAC:
68*4882a593Smuzhiyun case WM8940_DACVOL:
69*4882a593Smuzhiyun case WM8940_ADC:
70*4882a593Smuzhiyun case WM8940_ADCVOL:
71*4882a593Smuzhiyun case WM8940_NOTCH1:
72*4882a593Smuzhiyun case WM8940_NOTCH2:
73*4882a593Smuzhiyun case WM8940_NOTCH3:
74*4882a593Smuzhiyun case WM8940_NOTCH4:
75*4882a593Smuzhiyun case WM8940_NOTCH5:
76*4882a593Smuzhiyun case WM8940_NOTCH6:
77*4882a593Smuzhiyun case WM8940_NOTCH7:
78*4882a593Smuzhiyun case WM8940_NOTCH8:
79*4882a593Smuzhiyun case WM8940_DACLIM1:
80*4882a593Smuzhiyun case WM8940_DACLIM2:
81*4882a593Smuzhiyun case WM8940_ALC1:
82*4882a593Smuzhiyun case WM8940_ALC2:
83*4882a593Smuzhiyun case WM8940_ALC3:
84*4882a593Smuzhiyun case WM8940_NOISEGATE:
85*4882a593Smuzhiyun case WM8940_PLLN:
86*4882a593Smuzhiyun case WM8940_PLLK1:
87*4882a593Smuzhiyun case WM8940_PLLK2:
88*4882a593Smuzhiyun case WM8940_PLLK3:
89*4882a593Smuzhiyun case WM8940_ALC4:
90*4882a593Smuzhiyun case WM8940_INPUTCTL:
91*4882a593Smuzhiyun case WM8940_PGAGAIN:
92*4882a593Smuzhiyun case WM8940_ADCBOOST:
93*4882a593Smuzhiyun case WM8940_OUTPUTCTL:
94*4882a593Smuzhiyun case WM8940_SPKMIX:
95*4882a593Smuzhiyun case WM8940_SPKVOL:
96*4882a593Smuzhiyun case WM8940_MONOMIX:
97*4882a593Smuzhiyun return true;
98*4882a593Smuzhiyun default:
99*4882a593Smuzhiyun return false;
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun static const struct reg_default wm8940_reg_defaults[] = {
104*4882a593Smuzhiyun { 0x1, 0x0000 }, /* Power 1 */
105*4882a593Smuzhiyun { 0x2, 0x0000 }, /* Power 2 */
106*4882a593Smuzhiyun { 0x3, 0x0000 }, /* Power 3 */
107*4882a593Smuzhiyun { 0x4, 0x0010 }, /* Interface Control */
108*4882a593Smuzhiyun { 0x5, 0x0000 }, /* Companding Control */
109*4882a593Smuzhiyun { 0x6, 0x0140 }, /* Clock Control */
110*4882a593Smuzhiyun { 0x7, 0x0000 }, /* Additional Controls */
111*4882a593Smuzhiyun { 0x8, 0x0000 }, /* GPIO Control */
112*4882a593Smuzhiyun { 0x9, 0x0002 }, /* Auto Increment Control */
113*4882a593Smuzhiyun { 0xa, 0x0000 }, /* DAC Control */
114*4882a593Smuzhiyun { 0xb, 0x00FF }, /* DAC Volume */
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun { 0xe, 0x0100 }, /* ADC Control */
117*4882a593Smuzhiyun { 0xf, 0x00FF }, /* ADC Volume */
118*4882a593Smuzhiyun { 0x10, 0x0000 }, /* Notch Filter 1 Control 1 */
119*4882a593Smuzhiyun { 0x11, 0x0000 }, /* Notch Filter 1 Control 2 */
120*4882a593Smuzhiyun { 0x12, 0x0000 }, /* Notch Filter 2 Control 1 */
121*4882a593Smuzhiyun { 0x13, 0x0000 }, /* Notch Filter 2 Control 2 */
122*4882a593Smuzhiyun { 0x14, 0x0000 }, /* Notch Filter 3 Control 1 */
123*4882a593Smuzhiyun { 0x15, 0x0000 }, /* Notch Filter 3 Control 2 */
124*4882a593Smuzhiyun { 0x16, 0x0000 }, /* Notch Filter 4 Control 1 */
125*4882a593Smuzhiyun { 0x17, 0x0000 }, /* Notch Filter 4 Control 2 */
126*4882a593Smuzhiyun { 0x18, 0x0032 }, /* DAC Limit Control 1 */
127*4882a593Smuzhiyun { 0x19, 0x0000 }, /* DAC Limit Control 2 */
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun { 0x20, 0x0038 }, /* ALC Control 1 */
130*4882a593Smuzhiyun { 0x21, 0x000B }, /* ALC Control 2 */
131*4882a593Smuzhiyun { 0x22, 0x0032 }, /* ALC Control 3 */
132*4882a593Smuzhiyun { 0x23, 0x0000 }, /* Noise Gate */
133*4882a593Smuzhiyun { 0x24, 0x0041 }, /* PLLN */
134*4882a593Smuzhiyun { 0x25, 0x000C }, /* PLLK1 */
135*4882a593Smuzhiyun { 0x26, 0x0093 }, /* PLLK2 */
136*4882a593Smuzhiyun { 0x27, 0x00E9 }, /* PLLK3 */
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun { 0x2a, 0x0030 }, /* ALC Control 4 */
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun { 0x2c, 0x0002 }, /* Input Control */
141*4882a593Smuzhiyun { 0x2d, 0x0050 }, /* PGA Gain */
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun { 0x2f, 0x0002 }, /* ADC Boost Control */
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun { 0x31, 0x0002 }, /* Output Control */
146*4882a593Smuzhiyun { 0x32, 0x0000 }, /* Speaker Mixer Control */
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun { 0x36, 0x0079 }, /* Speaker Volume */
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun { 0x38, 0x0000 }, /* Mono Mixer Control */
151*4882a593Smuzhiyun };
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun static const char *wm8940_companding[] = { "Off", "NC", "u-law", "A-law" };
154*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(wm8940_adc_companding_enum,
155*4882a593Smuzhiyun WM8940_COMPANDINGCTL, 1, wm8940_companding);
156*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(wm8940_dac_companding_enum,
157*4882a593Smuzhiyun WM8940_COMPANDINGCTL, 3, wm8940_companding);
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun static const char *wm8940_alc_mode_text[] = {"ALC", "Limiter"};
160*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(wm8940_alc_mode_enum,
161*4882a593Smuzhiyun WM8940_ALC3, 8, wm8940_alc_mode_text);
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun static const char *wm8940_mic_bias_level_text[] = {"0.9", "0.65"};
164*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(wm8940_mic_bias_level_enum,
165*4882a593Smuzhiyun WM8940_INPUTCTL, 8, wm8940_mic_bias_level_text);
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun static const char *wm8940_filter_mode_text[] = {"Audio", "Application"};
168*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(wm8940_filter_mode_enum,
169*4882a593Smuzhiyun WM8940_ADC, 7, wm8940_filter_mode_text);
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun static DECLARE_TLV_DB_SCALE(wm8940_spk_vol_tlv, -5700, 100, 1);
172*4882a593Smuzhiyun static DECLARE_TLV_DB_SCALE(wm8940_att_tlv, -1000, 1000, 0);
173*4882a593Smuzhiyun static DECLARE_TLV_DB_SCALE(wm8940_pga_vol_tlv, -1200, 75, 0);
174*4882a593Smuzhiyun static DECLARE_TLV_DB_SCALE(wm8940_alc_min_tlv, -1200, 600, 0);
175*4882a593Smuzhiyun static DECLARE_TLV_DB_SCALE(wm8940_alc_max_tlv, 675, 600, 0);
176*4882a593Smuzhiyun static DECLARE_TLV_DB_SCALE(wm8940_alc_tar_tlv, -2250, 50, 0);
177*4882a593Smuzhiyun static DECLARE_TLV_DB_SCALE(wm8940_lim_boost_tlv, 0, 100, 0);
178*4882a593Smuzhiyun static DECLARE_TLV_DB_SCALE(wm8940_lim_thresh_tlv, -600, 100, 0);
179*4882a593Smuzhiyun static DECLARE_TLV_DB_SCALE(wm8940_adc_tlv, -12750, 50, 1);
180*4882a593Smuzhiyun static DECLARE_TLV_DB_SCALE(wm8940_capture_boost_vol_tlv, 0, 2000, 0);
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun static const struct snd_kcontrol_new wm8940_snd_controls[] = {
183*4882a593Smuzhiyun SOC_SINGLE("Digital Loopback Switch", WM8940_COMPANDINGCTL,
184*4882a593Smuzhiyun 6, 1, 0),
185*4882a593Smuzhiyun SOC_ENUM("DAC Companding", wm8940_dac_companding_enum),
186*4882a593Smuzhiyun SOC_ENUM("ADC Companding", wm8940_adc_companding_enum),
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun SOC_ENUM("ALC Mode", wm8940_alc_mode_enum),
189*4882a593Smuzhiyun SOC_SINGLE("ALC Switch", WM8940_ALC1, 8, 1, 0),
190*4882a593Smuzhiyun SOC_SINGLE_TLV("ALC Capture Max Gain", WM8940_ALC1,
191*4882a593Smuzhiyun 3, 7, 1, wm8940_alc_max_tlv),
192*4882a593Smuzhiyun SOC_SINGLE_TLV("ALC Capture Min Gain", WM8940_ALC1,
193*4882a593Smuzhiyun 0, 7, 0, wm8940_alc_min_tlv),
194*4882a593Smuzhiyun SOC_SINGLE_TLV("ALC Capture Target", WM8940_ALC2,
195*4882a593Smuzhiyun 0, 14, 0, wm8940_alc_tar_tlv),
196*4882a593Smuzhiyun SOC_SINGLE("ALC Capture Hold", WM8940_ALC2, 4, 10, 0),
197*4882a593Smuzhiyun SOC_SINGLE("ALC Capture Decay", WM8940_ALC3, 4, 10, 0),
198*4882a593Smuzhiyun SOC_SINGLE("ALC Capture Attach", WM8940_ALC3, 0, 10, 0),
199*4882a593Smuzhiyun SOC_SINGLE("ALC ZC Switch", WM8940_ALC4, 1, 1, 0),
200*4882a593Smuzhiyun SOC_SINGLE("ALC Capture Noise Gate Switch", WM8940_NOISEGATE,
201*4882a593Smuzhiyun 3, 1, 0),
202*4882a593Smuzhiyun SOC_SINGLE("ALC Capture Noise Gate Threshold", WM8940_NOISEGATE,
203*4882a593Smuzhiyun 0, 7, 0),
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun SOC_SINGLE("DAC Playback Limiter Switch", WM8940_DACLIM1, 8, 1, 0),
206*4882a593Smuzhiyun SOC_SINGLE("DAC Playback Limiter Attack", WM8940_DACLIM1, 0, 9, 0),
207*4882a593Smuzhiyun SOC_SINGLE("DAC Playback Limiter Decay", WM8940_DACLIM1, 4, 11, 0),
208*4882a593Smuzhiyun SOC_SINGLE_TLV("DAC Playback Limiter Threshold", WM8940_DACLIM2,
209*4882a593Smuzhiyun 4, 9, 1, wm8940_lim_thresh_tlv),
210*4882a593Smuzhiyun SOC_SINGLE_TLV("DAC Playback Limiter Boost", WM8940_DACLIM2,
211*4882a593Smuzhiyun 0, 12, 0, wm8940_lim_boost_tlv),
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun SOC_SINGLE("Capture PGA ZC Switch", WM8940_PGAGAIN, 7, 1, 0),
214*4882a593Smuzhiyun SOC_SINGLE_TLV("Capture PGA Volume", WM8940_PGAGAIN,
215*4882a593Smuzhiyun 0, 63, 0, wm8940_pga_vol_tlv),
216*4882a593Smuzhiyun SOC_SINGLE_TLV("Digital Playback Volume", WM8940_DACVOL,
217*4882a593Smuzhiyun 0, 255, 0, wm8940_adc_tlv),
218*4882a593Smuzhiyun SOC_SINGLE_TLV("Digital Capture Volume", WM8940_ADCVOL,
219*4882a593Smuzhiyun 0, 255, 0, wm8940_adc_tlv),
220*4882a593Smuzhiyun SOC_ENUM("Mic Bias Level", wm8940_mic_bias_level_enum),
221*4882a593Smuzhiyun SOC_SINGLE_TLV("Capture Boost Volue", WM8940_ADCBOOST,
222*4882a593Smuzhiyun 8, 1, 0, wm8940_capture_boost_vol_tlv),
223*4882a593Smuzhiyun SOC_SINGLE_TLV("Speaker Playback Volume", WM8940_SPKVOL,
224*4882a593Smuzhiyun 0, 63, 0, wm8940_spk_vol_tlv),
225*4882a593Smuzhiyun SOC_SINGLE("Speaker Playback Switch", WM8940_SPKVOL, 6, 1, 1),
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun SOC_SINGLE_TLV("Speaker Mixer Line Bypass Volume", WM8940_SPKVOL,
228*4882a593Smuzhiyun 8, 1, 1, wm8940_att_tlv),
229*4882a593Smuzhiyun SOC_SINGLE("Speaker Playback ZC Switch", WM8940_SPKVOL, 7, 1, 0),
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun SOC_SINGLE("Mono Out Switch", WM8940_MONOMIX, 6, 1, 1),
232*4882a593Smuzhiyun SOC_SINGLE_TLV("Mono Mixer Line Bypass Volume", WM8940_MONOMIX,
233*4882a593Smuzhiyun 7, 1, 1, wm8940_att_tlv),
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun SOC_SINGLE("High Pass Filter Switch", WM8940_ADC, 8, 1, 0),
236*4882a593Smuzhiyun SOC_ENUM("High Pass Filter Mode", wm8940_filter_mode_enum),
237*4882a593Smuzhiyun SOC_SINGLE("High Pass Filter Cut Off", WM8940_ADC, 4, 7, 0),
238*4882a593Smuzhiyun SOC_SINGLE("ADC Inversion Switch", WM8940_ADC, 0, 1, 0),
239*4882a593Smuzhiyun SOC_SINGLE("DAC Inversion Switch", WM8940_DAC, 0, 1, 0),
240*4882a593Smuzhiyun SOC_SINGLE("DAC Auto Mute Switch", WM8940_DAC, 2, 1, 0),
241*4882a593Smuzhiyun SOC_SINGLE("ZC Timeout Clock Switch", WM8940_ADDCNTRL, 0, 1, 0),
242*4882a593Smuzhiyun };
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun static const struct snd_kcontrol_new wm8940_speaker_mixer_controls[] = {
245*4882a593Smuzhiyun SOC_DAPM_SINGLE("Line Bypass Switch", WM8940_SPKMIX, 1, 1, 0),
246*4882a593Smuzhiyun SOC_DAPM_SINGLE("Aux Playback Switch", WM8940_SPKMIX, 5, 1, 0),
247*4882a593Smuzhiyun SOC_DAPM_SINGLE("PCM Playback Switch", WM8940_SPKMIX, 0, 1, 0),
248*4882a593Smuzhiyun };
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun static const struct snd_kcontrol_new wm8940_mono_mixer_controls[] = {
251*4882a593Smuzhiyun SOC_DAPM_SINGLE("Line Bypass Switch", WM8940_MONOMIX, 1, 1, 0),
252*4882a593Smuzhiyun SOC_DAPM_SINGLE("Aux Playback Switch", WM8940_MONOMIX, 2, 1, 0),
253*4882a593Smuzhiyun SOC_DAPM_SINGLE("PCM Playback Switch", WM8940_MONOMIX, 0, 1, 0),
254*4882a593Smuzhiyun };
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun static DECLARE_TLV_DB_SCALE(wm8940_boost_vol_tlv, -1500, 300, 1);
257*4882a593Smuzhiyun static const struct snd_kcontrol_new wm8940_input_boost_controls[] = {
258*4882a593Smuzhiyun SOC_DAPM_SINGLE("Mic PGA Switch", WM8940_PGAGAIN, 6, 1, 1),
259*4882a593Smuzhiyun SOC_DAPM_SINGLE_TLV("Aux Volume", WM8940_ADCBOOST,
260*4882a593Smuzhiyun 0, 7, 0, wm8940_boost_vol_tlv),
261*4882a593Smuzhiyun SOC_DAPM_SINGLE_TLV("Mic Volume", WM8940_ADCBOOST,
262*4882a593Smuzhiyun 4, 7, 0, wm8940_boost_vol_tlv),
263*4882a593Smuzhiyun };
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun static const struct snd_kcontrol_new wm8940_micpga_controls[] = {
266*4882a593Smuzhiyun SOC_DAPM_SINGLE("AUX Switch", WM8940_INPUTCTL, 2, 1, 0),
267*4882a593Smuzhiyun SOC_DAPM_SINGLE("MICP Switch", WM8940_INPUTCTL, 0, 1, 0),
268*4882a593Smuzhiyun SOC_DAPM_SINGLE("MICN Switch", WM8940_INPUTCTL, 1, 1, 0),
269*4882a593Smuzhiyun };
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun static const struct snd_soc_dapm_widget wm8940_dapm_widgets[] = {
272*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Speaker Mixer", WM8940_POWER3, 2, 0,
273*4882a593Smuzhiyun &wm8940_speaker_mixer_controls[0],
274*4882a593Smuzhiyun ARRAY_SIZE(wm8940_speaker_mixer_controls)),
275*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Mono Mixer", WM8940_POWER3, 3, 0,
276*4882a593Smuzhiyun &wm8940_mono_mixer_controls[0],
277*4882a593Smuzhiyun ARRAY_SIZE(wm8940_mono_mixer_controls)),
278*4882a593Smuzhiyun SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM8940_POWER3, 0, 0),
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun SND_SOC_DAPM_PGA("SpkN Out", WM8940_POWER3, 5, 0, NULL, 0),
281*4882a593Smuzhiyun SND_SOC_DAPM_PGA("SpkP Out", WM8940_POWER3, 6, 0, NULL, 0),
282*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Mono Out", WM8940_POWER3, 7, 0, NULL, 0),
283*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("MONOOUT"),
284*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPKOUTP"),
285*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPKOUTN"),
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Aux Input", WM8940_POWER1, 6, 0, NULL, 0),
288*4882a593Smuzhiyun SND_SOC_DAPM_ADC("ADC", "HiFi Capture", WM8940_POWER2, 0, 0),
289*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Mic PGA", WM8940_POWER2, 2, 0,
290*4882a593Smuzhiyun &wm8940_micpga_controls[0],
291*4882a593Smuzhiyun ARRAY_SIZE(wm8940_micpga_controls)),
292*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Boost Mixer", WM8940_POWER2, 4, 0,
293*4882a593Smuzhiyun &wm8940_input_boost_controls[0],
294*4882a593Smuzhiyun ARRAY_SIZE(wm8940_input_boost_controls)),
295*4882a593Smuzhiyun SND_SOC_DAPM_MICBIAS("Mic Bias", WM8940_POWER1, 4, 0),
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("MICN"),
298*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("MICP"),
299*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("AUX"),
300*4882a593Smuzhiyun };
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun static const struct snd_soc_dapm_route wm8940_dapm_routes[] = {
303*4882a593Smuzhiyun /* Mono output mixer */
304*4882a593Smuzhiyun {"Mono Mixer", "PCM Playback Switch", "DAC"},
305*4882a593Smuzhiyun {"Mono Mixer", "Aux Playback Switch", "Aux Input"},
306*4882a593Smuzhiyun {"Mono Mixer", "Line Bypass Switch", "Boost Mixer"},
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun /* Speaker output mixer */
309*4882a593Smuzhiyun {"Speaker Mixer", "PCM Playback Switch", "DAC"},
310*4882a593Smuzhiyun {"Speaker Mixer", "Aux Playback Switch", "Aux Input"},
311*4882a593Smuzhiyun {"Speaker Mixer", "Line Bypass Switch", "Boost Mixer"},
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun /* Outputs */
314*4882a593Smuzhiyun {"Mono Out", NULL, "Mono Mixer"},
315*4882a593Smuzhiyun {"MONOOUT", NULL, "Mono Out"},
316*4882a593Smuzhiyun {"SpkN Out", NULL, "Speaker Mixer"},
317*4882a593Smuzhiyun {"SpkP Out", NULL, "Speaker Mixer"},
318*4882a593Smuzhiyun {"SPKOUTN", NULL, "SpkN Out"},
319*4882a593Smuzhiyun {"SPKOUTP", NULL, "SpkP Out"},
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun /* Microphone PGA */
322*4882a593Smuzhiyun {"Mic PGA", "MICN Switch", "MICN"},
323*4882a593Smuzhiyun {"Mic PGA", "MICP Switch", "MICP"},
324*4882a593Smuzhiyun {"Mic PGA", "AUX Switch", "AUX"},
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun /* Boost Mixer */
327*4882a593Smuzhiyun {"Boost Mixer", "Mic PGA Switch", "Mic PGA"},
328*4882a593Smuzhiyun {"Boost Mixer", "Mic Volume", "MICP"},
329*4882a593Smuzhiyun {"Boost Mixer", "Aux Volume", "Aux Input"},
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun {"ADC", NULL, "Boost Mixer"},
332*4882a593Smuzhiyun };
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun #define wm8940_reset(c) snd_soc_component_write(c, WM8940_SOFTRESET, 0);
335*4882a593Smuzhiyun
wm8940_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)336*4882a593Smuzhiyun static int wm8940_set_dai_fmt(struct snd_soc_dai *codec_dai,
337*4882a593Smuzhiyun unsigned int fmt)
338*4882a593Smuzhiyun {
339*4882a593Smuzhiyun struct snd_soc_component *component = codec_dai->component;
340*4882a593Smuzhiyun u16 iface = snd_soc_component_read(component, WM8940_IFACE) & 0xFE67;
341*4882a593Smuzhiyun u16 clk = snd_soc_component_read(component, WM8940_CLOCK) & 0x1fe;
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
344*4882a593Smuzhiyun case SND_SOC_DAIFMT_CBM_CFM:
345*4882a593Smuzhiyun clk |= 1;
346*4882a593Smuzhiyun break;
347*4882a593Smuzhiyun case SND_SOC_DAIFMT_CBS_CFS:
348*4882a593Smuzhiyun break;
349*4882a593Smuzhiyun default:
350*4882a593Smuzhiyun return -EINVAL;
351*4882a593Smuzhiyun }
352*4882a593Smuzhiyun snd_soc_component_write(component, WM8940_CLOCK, clk);
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
355*4882a593Smuzhiyun case SND_SOC_DAIFMT_I2S:
356*4882a593Smuzhiyun iface |= (2 << 3);
357*4882a593Smuzhiyun break;
358*4882a593Smuzhiyun case SND_SOC_DAIFMT_LEFT_J:
359*4882a593Smuzhiyun iface |= (1 << 3);
360*4882a593Smuzhiyun break;
361*4882a593Smuzhiyun case SND_SOC_DAIFMT_RIGHT_J:
362*4882a593Smuzhiyun break;
363*4882a593Smuzhiyun case SND_SOC_DAIFMT_DSP_A:
364*4882a593Smuzhiyun iface |= (3 << 3);
365*4882a593Smuzhiyun break;
366*4882a593Smuzhiyun case SND_SOC_DAIFMT_DSP_B:
367*4882a593Smuzhiyun iface |= (3 << 3) | (1 << 7);
368*4882a593Smuzhiyun break;
369*4882a593Smuzhiyun }
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
372*4882a593Smuzhiyun case SND_SOC_DAIFMT_NB_NF:
373*4882a593Smuzhiyun break;
374*4882a593Smuzhiyun case SND_SOC_DAIFMT_NB_IF:
375*4882a593Smuzhiyun iface |= (1 << 7);
376*4882a593Smuzhiyun break;
377*4882a593Smuzhiyun case SND_SOC_DAIFMT_IB_NF:
378*4882a593Smuzhiyun iface |= (1 << 8);
379*4882a593Smuzhiyun break;
380*4882a593Smuzhiyun case SND_SOC_DAIFMT_IB_IF:
381*4882a593Smuzhiyun iface |= (1 << 8) | (1 << 7);
382*4882a593Smuzhiyun break;
383*4882a593Smuzhiyun }
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun snd_soc_component_write(component, WM8940_IFACE, iface);
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun return 0;
388*4882a593Smuzhiyun }
389*4882a593Smuzhiyun
wm8940_i2s_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)390*4882a593Smuzhiyun static int wm8940_i2s_hw_params(struct snd_pcm_substream *substream,
391*4882a593Smuzhiyun struct snd_pcm_hw_params *params,
392*4882a593Smuzhiyun struct snd_soc_dai *dai)
393*4882a593Smuzhiyun {
394*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
395*4882a593Smuzhiyun u16 iface = snd_soc_component_read(component, WM8940_IFACE) & 0xFD9F;
396*4882a593Smuzhiyun u16 addcntrl = snd_soc_component_read(component, WM8940_ADDCNTRL) & 0xFFF1;
397*4882a593Smuzhiyun u16 companding = snd_soc_component_read(component,
398*4882a593Smuzhiyun WM8940_COMPANDINGCTL) & 0xFFDF;
399*4882a593Smuzhiyun int ret;
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun /* LoutR control */
402*4882a593Smuzhiyun if (substream->stream == SNDRV_PCM_STREAM_CAPTURE
403*4882a593Smuzhiyun && params_channels(params) == 2)
404*4882a593Smuzhiyun iface |= (1 << 9);
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun switch (params_rate(params)) {
407*4882a593Smuzhiyun case 8000:
408*4882a593Smuzhiyun addcntrl |= (0x5 << 1);
409*4882a593Smuzhiyun break;
410*4882a593Smuzhiyun case 11025:
411*4882a593Smuzhiyun addcntrl |= (0x4 << 1);
412*4882a593Smuzhiyun break;
413*4882a593Smuzhiyun case 16000:
414*4882a593Smuzhiyun addcntrl |= (0x3 << 1);
415*4882a593Smuzhiyun break;
416*4882a593Smuzhiyun case 22050:
417*4882a593Smuzhiyun addcntrl |= (0x2 << 1);
418*4882a593Smuzhiyun break;
419*4882a593Smuzhiyun case 32000:
420*4882a593Smuzhiyun addcntrl |= (0x1 << 1);
421*4882a593Smuzhiyun break;
422*4882a593Smuzhiyun case 44100:
423*4882a593Smuzhiyun case 48000:
424*4882a593Smuzhiyun break;
425*4882a593Smuzhiyun }
426*4882a593Smuzhiyun ret = snd_soc_component_write(component, WM8940_ADDCNTRL, addcntrl);
427*4882a593Smuzhiyun if (ret)
428*4882a593Smuzhiyun goto error_ret;
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun switch (params_width(params)) {
431*4882a593Smuzhiyun case 8:
432*4882a593Smuzhiyun companding = companding | (1 << 5);
433*4882a593Smuzhiyun break;
434*4882a593Smuzhiyun case 16:
435*4882a593Smuzhiyun break;
436*4882a593Smuzhiyun case 20:
437*4882a593Smuzhiyun iface |= (1 << 5);
438*4882a593Smuzhiyun break;
439*4882a593Smuzhiyun case 24:
440*4882a593Smuzhiyun iface |= (2 << 5);
441*4882a593Smuzhiyun break;
442*4882a593Smuzhiyun case 32:
443*4882a593Smuzhiyun iface |= (3 << 5);
444*4882a593Smuzhiyun break;
445*4882a593Smuzhiyun }
446*4882a593Smuzhiyun ret = snd_soc_component_write(component, WM8940_COMPANDINGCTL, companding);
447*4882a593Smuzhiyun if (ret)
448*4882a593Smuzhiyun goto error_ret;
449*4882a593Smuzhiyun ret = snd_soc_component_write(component, WM8940_IFACE, iface);
450*4882a593Smuzhiyun
451*4882a593Smuzhiyun error_ret:
452*4882a593Smuzhiyun return ret;
453*4882a593Smuzhiyun }
454*4882a593Smuzhiyun
wm8940_mute(struct snd_soc_dai * dai,int mute,int direction)455*4882a593Smuzhiyun static int wm8940_mute(struct snd_soc_dai *dai, int mute, int direction)
456*4882a593Smuzhiyun {
457*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
458*4882a593Smuzhiyun u16 mute_reg = snd_soc_component_read(component, WM8940_DAC) & 0xffbf;
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun if (mute)
461*4882a593Smuzhiyun mute_reg |= 0x40;
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun return snd_soc_component_write(component, WM8940_DAC, mute_reg);
464*4882a593Smuzhiyun }
465*4882a593Smuzhiyun
wm8940_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)466*4882a593Smuzhiyun static int wm8940_set_bias_level(struct snd_soc_component *component,
467*4882a593Smuzhiyun enum snd_soc_bias_level level)
468*4882a593Smuzhiyun {
469*4882a593Smuzhiyun struct wm8940_priv *wm8940 = snd_soc_component_get_drvdata(component);
470*4882a593Smuzhiyun u16 val;
471*4882a593Smuzhiyun u16 pwr_reg = snd_soc_component_read(component, WM8940_POWER1) & 0x1F0;
472*4882a593Smuzhiyun int ret = 0;
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun switch (level) {
475*4882a593Smuzhiyun case SND_SOC_BIAS_ON:
476*4882a593Smuzhiyun /* ensure bufioen and biasen */
477*4882a593Smuzhiyun pwr_reg |= (1 << 2) | (1 << 3);
478*4882a593Smuzhiyun /* Enable thermal shutdown */
479*4882a593Smuzhiyun val = snd_soc_component_read(component, WM8940_OUTPUTCTL);
480*4882a593Smuzhiyun ret = snd_soc_component_write(component, WM8940_OUTPUTCTL, val | 0x2);
481*4882a593Smuzhiyun if (ret)
482*4882a593Smuzhiyun break;
483*4882a593Smuzhiyun /* set vmid to 75k */
484*4882a593Smuzhiyun ret = snd_soc_component_write(component, WM8940_POWER1, pwr_reg | 0x1);
485*4882a593Smuzhiyun break;
486*4882a593Smuzhiyun case SND_SOC_BIAS_PREPARE:
487*4882a593Smuzhiyun /* ensure bufioen and biasen */
488*4882a593Smuzhiyun pwr_reg |= (1 << 2) | (1 << 3);
489*4882a593Smuzhiyun ret = snd_soc_component_write(component, WM8940_POWER1, pwr_reg | 0x1);
490*4882a593Smuzhiyun break;
491*4882a593Smuzhiyun case SND_SOC_BIAS_STANDBY:
492*4882a593Smuzhiyun if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
493*4882a593Smuzhiyun ret = regcache_sync(wm8940->regmap);
494*4882a593Smuzhiyun if (ret < 0) {
495*4882a593Smuzhiyun dev_err(component->dev, "Failed to sync cache: %d\n", ret);
496*4882a593Smuzhiyun return ret;
497*4882a593Smuzhiyun }
498*4882a593Smuzhiyun }
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun /* ensure bufioen and biasen */
501*4882a593Smuzhiyun pwr_reg |= (1 << 2) | (1 << 3);
502*4882a593Smuzhiyun /* set vmid to 300k for standby */
503*4882a593Smuzhiyun ret = snd_soc_component_write(component, WM8940_POWER1, pwr_reg | 0x2);
504*4882a593Smuzhiyun break;
505*4882a593Smuzhiyun case SND_SOC_BIAS_OFF:
506*4882a593Smuzhiyun ret = snd_soc_component_write(component, WM8940_POWER1, pwr_reg);
507*4882a593Smuzhiyun break;
508*4882a593Smuzhiyun }
509*4882a593Smuzhiyun
510*4882a593Smuzhiyun return ret;
511*4882a593Smuzhiyun }
512*4882a593Smuzhiyun
513*4882a593Smuzhiyun struct pll_ {
514*4882a593Smuzhiyun unsigned int pre_scale:2;
515*4882a593Smuzhiyun unsigned int n:4;
516*4882a593Smuzhiyun unsigned int k;
517*4882a593Smuzhiyun };
518*4882a593Smuzhiyun
519*4882a593Smuzhiyun static struct pll_ pll_div;
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun /* The size in bits of the pll divide multiplied by 10
522*4882a593Smuzhiyun * to allow rounding later */
523*4882a593Smuzhiyun #define FIXED_PLL_SIZE ((1 << 24) * 10)
pll_factors(unsigned int target,unsigned int source)524*4882a593Smuzhiyun static void pll_factors(unsigned int target, unsigned int source)
525*4882a593Smuzhiyun {
526*4882a593Smuzhiyun unsigned long long Kpart;
527*4882a593Smuzhiyun unsigned int K, Ndiv, Nmod;
528*4882a593Smuzhiyun /* The left shift ist to avoid accuracy loss when right shifting */
529*4882a593Smuzhiyun Ndiv = target / source;
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun if (Ndiv > 12) {
532*4882a593Smuzhiyun source <<= 1;
533*4882a593Smuzhiyun /* Multiply by 2 */
534*4882a593Smuzhiyun pll_div.pre_scale = 0;
535*4882a593Smuzhiyun Ndiv = target / source;
536*4882a593Smuzhiyun } else if (Ndiv < 3) {
537*4882a593Smuzhiyun source >>= 2;
538*4882a593Smuzhiyun /* Divide by 4 */
539*4882a593Smuzhiyun pll_div.pre_scale = 3;
540*4882a593Smuzhiyun Ndiv = target / source;
541*4882a593Smuzhiyun } else if (Ndiv < 6) {
542*4882a593Smuzhiyun source >>= 1;
543*4882a593Smuzhiyun /* divide by 2 */
544*4882a593Smuzhiyun pll_div.pre_scale = 2;
545*4882a593Smuzhiyun Ndiv = target / source;
546*4882a593Smuzhiyun } else
547*4882a593Smuzhiyun pll_div.pre_scale = 1;
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun if ((Ndiv < 6) || (Ndiv > 12))
550*4882a593Smuzhiyun printk(KERN_WARNING
551*4882a593Smuzhiyun "WM8940 N value %d outwith recommended range!d\n",
552*4882a593Smuzhiyun Ndiv);
553*4882a593Smuzhiyun
554*4882a593Smuzhiyun pll_div.n = Ndiv;
555*4882a593Smuzhiyun Nmod = target % source;
556*4882a593Smuzhiyun Kpart = FIXED_PLL_SIZE * (long long)Nmod;
557*4882a593Smuzhiyun
558*4882a593Smuzhiyun do_div(Kpart, source);
559*4882a593Smuzhiyun
560*4882a593Smuzhiyun K = Kpart & 0xFFFFFFFF;
561*4882a593Smuzhiyun
562*4882a593Smuzhiyun /* Check if we need to round */
563*4882a593Smuzhiyun if ((K % 10) >= 5)
564*4882a593Smuzhiyun K += 5;
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun /* Move down to proper range now rounding is done */
567*4882a593Smuzhiyun K /= 10;
568*4882a593Smuzhiyun
569*4882a593Smuzhiyun pll_div.k = K;
570*4882a593Smuzhiyun }
571*4882a593Smuzhiyun
572*4882a593Smuzhiyun /* Untested at the moment */
wm8940_set_dai_pll(struct snd_soc_dai * codec_dai,int pll_id,int source,unsigned int freq_in,unsigned int freq_out)573*4882a593Smuzhiyun static int wm8940_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
574*4882a593Smuzhiyun int source, unsigned int freq_in, unsigned int freq_out)
575*4882a593Smuzhiyun {
576*4882a593Smuzhiyun struct snd_soc_component *component = codec_dai->component;
577*4882a593Smuzhiyun u16 reg;
578*4882a593Smuzhiyun
579*4882a593Smuzhiyun /* Turn off PLL */
580*4882a593Smuzhiyun reg = snd_soc_component_read(component, WM8940_POWER1);
581*4882a593Smuzhiyun snd_soc_component_write(component, WM8940_POWER1, reg & 0x1df);
582*4882a593Smuzhiyun
583*4882a593Smuzhiyun if (freq_in == 0 || freq_out == 0) {
584*4882a593Smuzhiyun /* Clock CODEC directly from MCLK */
585*4882a593Smuzhiyun reg = snd_soc_component_read(component, WM8940_CLOCK);
586*4882a593Smuzhiyun snd_soc_component_write(component, WM8940_CLOCK, reg & 0x0ff);
587*4882a593Smuzhiyun /* Pll power down */
588*4882a593Smuzhiyun snd_soc_component_write(component, WM8940_PLLN, (1 << 7));
589*4882a593Smuzhiyun return 0;
590*4882a593Smuzhiyun }
591*4882a593Smuzhiyun
592*4882a593Smuzhiyun /* Pll is followed by a frequency divide by 4 */
593*4882a593Smuzhiyun pll_factors(freq_out*4, freq_in);
594*4882a593Smuzhiyun if (pll_div.k)
595*4882a593Smuzhiyun snd_soc_component_write(component, WM8940_PLLN,
596*4882a593Smuzhiyun (pll_div.pre_scale << 4) | pll_div.n | (1 << 6));
597*4882a593Smuzhiyun else /* No factional component */
598*4882a593Smuzhiyun snd_soc_component_write(component, WM8940_PLLN,
599*4882a593Smuzhiyun (pll_div.pre_scale << 4) | pll_div.n);
600*4882a593Smuzhiyun snd_soc_component_write(component, WM8940_PLLK1, pll_div.k >> 18);
601*4882a593Smuzhiyun snd_soc_component_write(component, WM8940_PLLK2, (pll_div.k >> 9) & 0x1ff);
602*4882a593Smuzhiyun snd_soc_component_write(component, WM8940_PLLK3, pll_div.k & 0x1ff);
603*4882a593Smuzhiyun /* Enable the PLL */
604*4882a593Smuzhiyun reg = snd_soc_component_read(component, WM8940_POWER1);
605*4882a593Smuzhiyun snd_soc_component_write(component, WM8940_POWER1, reg | 0x020);
606*4882a593Smuzhiyun
607*4882a593Smuzhiyun /* Run CODEC from PLL instead of MCLK */
608*4882a593Smuzhiyun reg = snd_soc_component_read(component, WM8940_CLOCK);
609*4882a593Smuzhiyun snd_soc_component_write(component, WM8940_CLOCK, reg | 0x100);
610*4882a593Smuzhiyun
611*4882a593Smuzhiyun return 0;
612*4882a593Smuzhiyun }
613*4882a593Smuzhiyun
wm8940_set_dai_sysclk(struct snd_soc_dai * codec_dai,int clk_id,unsigned int freq,int dir)614*4882a593Smuzhiyun static int wm8940_set_dai_sysclk(struct snd_soc_dai *codec_dai,
615*4882a593Smuzhiyun int clk_id, unsigned int freq, int dir)
616*4882a593Smuzhiyun {
617*4882a593Smuzhiyun struct snd_soc_component *component = codec_dai->component;
618*4882a593Smuzhiyun struct wm8940_priv *wm8940 = snd_soc_component_get_drvdata(component);
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun switch (freq) {
621*4882a593Smuzhiyun case 11289600:
622*4882a593Smuzhiyun case 12000000:
623*4882a593Smuzhiyun case 12288000:
624*4882a593Smuzhiyun case 16934400:
625*4882a593Smuzhiyun case 18432000:
626*4882a593Smuzhiyun wm8940->sysclk = freq;
627*4882a593Smuzhiyun return 0;
628*4882a593Smuzhiyun }
629*4882a593Smuzhiyun return -EINVAL;
630*4882a593Smuzhiyun }
631*4882a593Smuzhiyun
wm8940_set_dai_clkdiv(struct snd_soc_dai * codec_dai,int div_id,int div)632*4882a593Smuzhiyun static int wm8940_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
633*4882a593Smuzhiyun int div_id, int div)
634*4882a593Smuzhiyun {
635*4882a593Smuzhiyun struct snd_soc_component *component = codec_dai->component;
636*4882a593Smuzhiyun u16 reg;
637*4882a593Smuzhiyun int ret = 0;
638*4882a593Smuzhiyun
639*4882a593Smuzhiyun switch (div_id) {
640*4882a593Smuzhiyun case WM8940_BCLKDIV:
641*4882a593Smuzhiyun reg = snd_soc_component_read(component, WM8940_CLOCK) & 0xFFE3;
642*4882a593Smuzhiyun ret = snd_soc_component_write(component, WM8940_CLOCK, reg | (div << 2));
643*4882a593Smuzhiyun break;
644*4882a593Smuzhiyun case WM8940_MCLKDIV:
645*4882a593Smuzhiyun reg = snd_soc_component_read(component, WM8940_CLOCK) & 0xFF1F;
646*4882a593Smuzhiyun ret = snd_soc_component_write(component, WM8940_CLOCK, reg | (div << 5));
647*4882a593Smuzhiyun break;
648*4882a593Smuzhiyun case WM8940_OPCLKDIV:
649*4882a593Smuzhiyun reg = snd_soc_component_read(component, WM8940_GPIO) & 0xFFCF;
650*4882a593Smuzhiyun ret = snd_soc_component_write(component, WM8940_GPIO, reg | (div << 4));
651*4882a593Smuzhiyun break;
652*4882a593Smuzhiyun }
653*4882a593Smuzhiyun return ret;
654*4882a593Smuzhiyun }
655*4882a593Smuzhiyun
656*4882a593Smuzhiyun #define WM8940_RATES SNDRV_PCM_RATE_8000_48000
657*4882a593Smuzhiyun
658*4882a593Smuzhiyun #define WM8940_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
659*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S16_LE | \
660*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S20_3LE | \
661*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S24_LE | \
662*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S32_LE)
663*4882a593Smuzhiyun
664*4882a593Smuzhiyun static const struct snd_soc_dai_ops wm8940_dai_ops = {
665*4882a593Smuzhiyun .hw_params = wm8940_i2s_hw_params,
666*4882a593Smuzhiyun .set_sysclk = wm8940_set_dai_sysclk,
667*4882a593Smuzhiyun .mute_stream = wm8940_mute,
668*4882a593Smuzhiyun .set_fmt = wm8940_set_dai_fmt,
669*4882a593Smuzhiyun .set_clkdiv = wm8940_set_dai_clkdiv,
670*4882a593Smuzhiyun .set_pll = wm8940_set_dai_pll,
671*4882a593Smuzhiyun .no_capture_mute = 1,
672*4882a593Smuzhiyun };
673*4882a593Smuzhiyun
674*4882a593Smuzhiyun static struct snd_soc_dai_driver wm8940_dai = {
675*4882a593Smuzhiyun .name = "wm8940-hifi",
676*4882a593Smuzhiyun .playback = {
677*4882a593Smuzhiyun .stream_name = "Playback",
678*4882a593Smuzhiyun .channels_min = 1,
679*4882a593Smuzhiyun .channels_max = 2,
680*4882a593Smuzhiyun .rates = WM8940_RATES,
681*4882a593Smuzhiyun .formats = WM8940_FORMATS,
682*4882a593Smuzhiyun },
683*4882a593Smuzhiyun .capture = {
684*4882a593Smuzhiyun .stream_name = "Capture",
685*4882a593Smuzhiyun .channels_min = 1,
686*4882a593Smuzhiyun .channels_max = 2,
687*4882a593Smuzhiyun .rates = WM8940_RATES,
688*4882a593Smuzhiyun .formats = WM8940_FORMATS,
689*4882a593Smuzhiyun },
690*4882a593Smuzhiyun .ops = &wm8940_dai_ops,
691*4882a593Smuzhiyun .symmetric_rates = 1,
692*4882a593Smuzhiyun };
693*4882a593Smuzhiyun
wm8940_probe(struct snd_soc_component * component)694*4882a593Smuzhiyun static int wm8940_probe(struct snd_soc_component *component)
695*4882a593Smuzhiyun {
696*4882a593Smuzhiyun struct wm8940_setup_data *pdata = component->dev->platform_data;
697*4882a593Smuzhiyun int ret;
698*4882a593Smuzhiyun u16 reg;
699*4882a593Smuzhiyun
700*4882a593Smuzhiyun ret = wm8940_reset(component);
701*4882a593Smuzhiyun if (ret < 0) {
702*4882a593Smuzhiyun dev_err(component->dev, "Failed to issue reset\n");
703*4882a593Smuzhiyun return ret;
704*4882a593Smuzhiyun }
705*4882a593Smuzhiyun
706*4882a593Smuzhiyun snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
707*4882a593Smuzhiyun
708*4882a593Smuzhiyun ret = snd_soc_component_write(component, WM8940_POWER1, 0x180);
709*4882a593Smuzhiyun if (ret < 0)
710*4882a593Smuzhiyun return ret;
711*4882a593Smuzhiyun
712*4882a593Smuzhiyun if (!pdata)
713*4882a593Smuzhiyun dev_warn(component->dev, "No platform data supplied\n");
714*4882a593Smuzhiyun else {
715*4882a593Smuzhiyun reg = snd_soc_component_read(component, WM8940_OUTPUTCTL);
716*4882a593Smuzhiyun ret = snd_soc_component_write(component, WM8940_OUTPUTCTL, reg | pdata->vroi);
717*4882a593Smuzhiyun if (ret < 0)
718*4882a593Smuzhiyun return ret;
719*4882a593Smuzhiyun }
720*4882a593Smuzhiyun
721*4882a593Smuzhiyun return ret;
722*4882a593Smuzhiyun }
723*4882a593Smuzhiyun
724*4882a593Smuzhiyun static const struct snd_soc_component_driver soc_component_dev_wm8940 = {
725*4882a593Smuzhiyun .probe = wm8940_probe,
726*4882a593Smuzhiyun .set_bias_level = wm8940_set_bias_level,
727*4882a593Smuzhiyun .controls = wm8940_snd_controls,
728*4882a593Smuzhiyun .num_controls = ARRAY_SIZE(wm8940_snd_controls),
729*4882a593Smuzhiyun .dapm_widgets = wm8940_dapm_widgets,
730*4882a593Smuzhiyun .num_dapm_widgets = ARRAY_SIZE(wm8940_dapm_widgets),
731*4882a593Smuzhiyun .dapm_routes = wm8940_dapm_routes,
732*4882a593Smuzhiyun .num_dapm_routes = ARRAY_SIZE(wm8940_dapm_routes),
733*4882a593Smuzhiyun .suspend_bias_off = 1,
734*4882a593Smuzhiyun .idle_bias_on = 1,
735*4882a593Smuzhiyun .use_pmdown_time = 1,
736*4882a593Smuzhiyun .endianness = 1,
737*4882a593Smuzhiyun .non_legacy_dai_naming = 1,
738*4882a593Smuzhiyun };
739*4882a593Smuzhiyun
740*4882a593Smuzhiyun static const struct regmap_config wm8940_regmap = {
741*4882a593Smuzhiyun .reg_bits = 8,
742*4882a593Smuzhiyun .val_bits = 16,
743*4882a593Smuzhiyun
744*4882a593Smuzhiyun .max_register = WM8940_MONOMIX,
745*4882a593Smuzhiyun .reg_defaults = wm8940_reg_defaults,
746*4882a593Smuzhiyun .num_reg_defaults = ARRAY_SIZE(wm8940_reg_defaults),
747*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
748*4882a593Smuzhiyun
749*4882a593Smuzhiyun .readable_reg = wm8940_readable_register,
750*4882a593Smuzhiyun .volatile_reg = wm8940_volatile_register,
751*4882a593Smuzhiyun };
752*4882a593Smuzhiyun
wm8940_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)753*4882a593Smuzhiyun static int wm8940_i2c_probe(struct i2c_client *i2c,
754*4882a593Smuzhiyun const struct i2c_device_id *id)
755*4882a593Smuzhiyun {
756*4882a593Smuzhiyun struct wm8940_priv *wm8940;
757*4882a593Smuzhiyun int ret;
758*4882a593Smuzhiyun
759*4882a593Smuzhiyun wm8940 = devm_kzalloc(&i2c->dev, sizeof(struct wm8940_priv),
760*4882a593Smuzhiyun GFP_KERNEL);
761*4882a593Smuzhiyun if (wm8940 == NULL)
762*4882a593Smuzhiyun return -ENOMEM;
763*4882a593Smuzhiyun
764*4882a593Smuzhiyun wm8940->regmap = devm_regmap_init_i2c(i2c, &wm8940_regmap);
765*4882a593Smuzhiyun if (IS_ERR(wm8940->regmap))
766*4882a593Smuzhiyun return PTR_ERR(wm8940->regmap);
767*4882a593Smuzhiyun
768*4882a593Smuzhiyun i2c_set_clientdata(i2c, wm8940);
769*4882a593Smuzhiyun
770*4882a593Smuzhiyun ret = devm_snd_soc_register_component(&i2c->dev,
771*4882a593Smuzhiyun &soc_component_dev_wm8940, &wm8940_dai, 1);
772*4882a593Smuzhiyun
773*4882a593Smuzhiyun return ret;
774*4882a593Smuzhiyun }
775*4882a593Smuzhiyun
776*4882a593Smuzhiyun static const struct i2c_device_id wm8940_i2c_id[] = {
777*4882a593Smuzhiyun { "wm8940", 0 },
778*4882a593Smuzhiyun { }
779*4882a593Smuzhiyun };
780*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, wm8940_i2c_id);
781*4882a593Smuzhiyun
782*4882a593Smuzhiyun static struct i2c_driver wm8940_i2c_driver = {
783*4882a593Smuzhiyun .driver = {
784*4882a593Smuzhiyun .name = "wm8940",
785*4882a593Smuzhiyun },
786*4882a593Smuzhiyun .probe = wm8940_i2c_probe,
787*4882a593Smuzhiyun .id_table = wm8940_i2c_id,
788*4882a593Smuzhiyun };
789*4882a593Smuzhiyun
790*4882a593Smuzhiyun module_i2c_driver(wm8940_i2c_driver);
791*4882a593Smuzhiyun
792*4882a593Smuzhiyun MODULE_DESCRIPTION("ASoC WM8940 driver");
793*4882a593Smuzhiyun MODULE_AUTHOR("Jonathan Cameron");
794*4882a593Smuzhiyun MODULE_LICENSE("GPL");
795