xref: /OK3568_Linux_fs/kernel/sound/soc/codecs/wm8510.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * wm8510.c  --  WM8510 ALSA Soc Audio driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright 2006 Wolfson Microelectronics PLC.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Author: Liam Girdwood <lrg@slimlogic.co.uk>
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/moduleparam.h>
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/init.h>
14*4882a593Smuzhiyun #include <linux/delay.h>
15*4882a593Smuzhiyun #include <linux/pm.h>
16*4882a593Smuzhiyun #include <linux/i2c.h>
17*4882a593Smuzhiyun #include <linux/spi/spi.h>
18*4882a593Smuzhiyun #include <linux/slab.h>
19*4882a593Smuzhiyun #include <linux/of_device.h>
20*4882a593Smuzhiyun #include <linux/regmap.h>
21*4882a593Smuzhiyun #include <sound/core.h>
22*4882a593Smuzhiyun #include <sound/pcm.h>
23*4882a593Smuzhiyun #include <sound/pcm_params.h>
24*4882a593Smuzhiyun #include <sound/soc.h>
25*4882a593Smuzhiyun #include <sound/initval.h>
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #include "wm8510.h"
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun /*
30*4882a593Smuzhiyun  * wm8510 register cache
31*4882a593Smuzhiyun  * We can't read the WM8510 register space when we are
32*4882a593Smuzhiyun  * using 2 wire for device control, so we cache them instead.
33*4882a593Smuzhiyun  */
34*4882a593Smuzhiyun static const struct reg_default wm8510_reg_defaults[] = {
35*4882a593Smuzhiyun 	{  1, 0x0000 },
36*4882a593Smuzhiyun 	{  2, 0x0000 },
37*4882a593Smuzhiyun 	{  3, 0x0000 },
38*4882a593Smuzhiyun 	{  4, 0x0050 },
39*4882a593Smuzhiyun 	{  5, 0x0000 },
40*4882a593Smuzhiyun 	{  6, 0x0140 },
41*4882a593Smuzhiyun 	{  7, 0x0000 },
42*4882a593Smuzhiyun 	{  8, 0x0000 },
43*4882a593Smuzhiyun 	{  9, 0x0000 },
44*4882a593Smuzhiyun 	{ 10, 0x0000 },
45*4882a593Smuzhiyun 	{ 11, 0x00ff },
46*4882a593Smuzhiyun 	{ 12, 0x0000 },
47*4882a593Smuzhiyun 	{ 13, 0x0000 },
48*4882a593Smuzhiyun 	{ 14, 0x0100 },
49*4882a593Smuzhiyun 	{ 15, 0x00ff },
50*4882a593Smuzhiyun 	{ 16, 0x0000 },
51*4882a593Smuzhiyun 	{ 17, 0x0000 },
52*4882a593Smuzhiyun 	{ 18, 0x012c },
53*4882a593Smuzhiyun 	{ 19, 0x002c },
54*4882a593Smuzhiyun 	{ 20, 0x002c },
55*4882a593Smuzhiyun 	{ 21, 0x002c },
56*4882a593Smuzhiyun 	{ 22, 0x002c },
57*4882a593Smuzhiyun 	{ 23, 0x0000 },
58*4882a593Smuzhiyun 	{ 24, 0x0032 },
59*4882a593Smuzhiyun 	{ 25, 0x0000 },
60*4882a593Smuzhiyun 	{ 26, 0x0000 },
61*4882a593Smuzhiyun 	{ 27, 0x0000 },
62*4882a593Smuzhiyun 	{ 28, 0x0000 },
63*4882a593Smuzhiyun 	{ 29, 0x0000 },
64*4882a593Smuzhiyun 	{ 30, 0x0000 },
65*4882a593Smuzhiyun 	{ 31, 0x0000 },
66*4882a593Smuzhiyun 	{ 32, 0x0038 },
67*4882a593Smuzhiyun 	{ 33, 0x000b },
68*4882a593Smuzhiyun 	{ 34, 0x0032 },
69*4882a593Smuzhiyun 	{ 35, 0x0000 },
70*4882a593Smuzhiyun 	{ 36, 0x0008 },
71*4882a593Smuzhiyun 	{ 37, 0x000c },
72*4882a593Smuzhiyun 	{ 38, 0x0093 },
73*4882a593Smuzhiyun 	{ 39, 0x00e9 },
74*4882a593Smuzhiyun 	{ 40, 0x0000 },
75*4882a593Smuzhiyun 	{ 41, 0x0000 },
76*4882a593Smuzhiyun 	{ 42, 0x0000 },
77*4882a593Smuzhiyun 	{ 43, 0x0000 },
78*4882a593Smuzhiyun 	{ 44, 0x0003 },
79*4882a593Smuzhiyun 	{ 45, 0x0010 },
80*4882a593Smuzhiyun 	{ 46, 0x0000 },
81*4882a593Smuzhiyun 	{ 47, 0x0000 },
82*4882a593Smuzhiyun 	{ 48, 0x0000 },
83*4882a593Smuzhiyun 	{ 49, 0x0002 },
84*4882a593Smuzhiyun 	{ 50, 0x0001 },
85*4882a593Smuzhiyun 	{ 51, 0x0000 },
86*4882a593Smuzhiyun 	{ 52, 0x0000 },
87*4882a593Smuzhiyun 	{ 53, 0x0000 },
88*4882a593Smuzhiyun 	{ 54, 0x0039 },
89*4882a593Smuzhiyun 	{ 55, 0x0000 },
90*4882a593Smuzhiyun 	{ 56, 0x0001 },
91*4882a593Smuzhiyun };
92*4882a593Smuzhiyun 
wm8510_volatile(struct device * dev,unsigned int reg)93*4882a593Smuzhiyun static bool wm8510_volatile(struct device *dev, unsigned int reg)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun 	switch (reg) {
96*4882a593Smuzhiyun 	case WM8510_RESET:
97*4882a593Smuzhiyun 		return true;
98*4882a593Smuzhiyun 	default:
99*4882a593Smuzhiyun 		return false;
100*4882a593Smuzhiyun 	}
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun #define WM8510_POWER1_BIASEN  0x08
104*4882a593Smuzhiyun #define WM8510_POWER1_BUFIOEN 0x10
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun #define wm8510_reset(c)	snd_soc_component_write(c, WM8510_RESET, 0)
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun /* codec private data */
109*4882a593Smuzhiyun struct wm8510_priv {
110*4882a593Smuzhiyun 	struct regmap *regmap;
111*4882a593Smuzhiyun };
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun static const char *wm8510_companding[] = { "Off", "NC", "u-law", "A-law" };
114*4882a593Smuzhiyun static const char *wm8510_deemp[] = { "None", "32kHz", "44.1kHz", "48kHz" };
115*4882a593Smuzhiyun static const char *wm8510_alc[] = { "ALC", "Limiter" };
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun static const struct soc_enum wm8510_enum[] = {
118*4882a593Smuzhiyun 	SOC_ENUM_SINGLE(WM8510_COMP, 1, 4, wm8510_companding), /* adc */
119*4882a593Smuzhiyun 	SOC_ENUM_SINGLE(WM8510_COMP, 3, 4, wm8510_companding), /* dac */
120*4882a593Smuzhiyun 	SOC_ENUM_SINGLE(WM8510_DAC,  4, 4, wm8510_deemp),
121*4882a593Smuzhiyun 	SOC_ENUM_SINGLE(WM8510_ALC3,  8, 2, wm8510_alc),
122*4882a593Smuzhiyun };
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun static const struct snd_kcontrol_new wm8510_snd_controls[] = {
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun SOC_SINGLE("Digital Loopback Switch", WM8510_COMP, 0, 1, 0),
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun SOC_ENUM("DAC Companding", wm8510_enum[1]),
129*4882a593Smuzhiyun SOC_ENUM("ADC Companding", wm8510_enum[0]),
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun SOC_ENUM("Playback De-emphasis", wm8510_enum[2]),
132*4882a593Smuzhiyun SOC_SINGLE("DAC Inversion Switch", WM8510_DAC, 0, 1, 0),
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun SOC_SINGLE("Master Playback Volume", WM8510_DACVOL, 0, 127, 0),
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun SOC_SINGLE("High Pass Filter Switch", WM8510_ADC, 8, 1, 0),
137*4882a593Smuzhiyun SOC_SINGLE("High Pass Cut Off", WM8510_ADC, 4, 7, 0),
138*4882a593Smuzhiyun SOC_SINGLE("ADC Inversion Switch", WM8510_COMP, 0, 1, 0),
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun SOC_SINGLE("Capture Volume", WM8510_ADCVOL,  0, 127, 0),
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun SOC_SINGLE("DAC Playback Limiter Switch", WM8510_DACLIM1,  8, 1, 0),
143*4882a593Smuzhiyun SOC_SINGLE("DAC Playback Limiter Decay", WM8510_DACLIM1,  4, 15, 0),
144*4882a593Smuzhiyun SOC_SINGLE("DAC Playback Limiter Attack", WM8510_DACLIM1,  0, 15, 0),
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun SOC_SINGLE("DAC Playback Limiter Threshold", WM8510_DACLIM2,  4, 7, 0),
147*4882a593Smuzhiyun SOC_SINGLE("DAC Playback Limiter Boost", WM8510_DACLIM2,  0, 15, 0),
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun SOC_SINGLE("ALC Enable Switch", WM8510_ALC1,  8, 1, 0),
150*4882a593Smuzhiyun SOC_SINGLE("ALC Capture Max Gain", WM8510_ALC1,  3, 7, 0),
151*4882a593Smuzhiyun SOC_SINGLE("ALC Capture Min Gain", WM8510_ALC1,  0, 7, 0),
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun SOC_SINGLE("ALC Capture ZC Switch", WM8510_ALC2,  8, 1, 0),
154*4882a593Smuzhiyun SOC_SINGLE("ALC Capture Hold", WM8510_ALC2,  4, 7, 0),
155*4882a593Smuzhiyun SOC_SINGLE("ALC Capture Target", WM8510_ALC2,  0, 15, 0),
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun SOC_ENUM("ALC Capture Mode", wm8510_enum[3]),
158*4882a593Smuzhiyun SOC_SINGLE("ALC Capture Decay", WM8510_ALC3,  4, 15, 0),
159*4882a593Smuzhiyun SOC_SINGLE("ALC Capture Attack", WM8510_ALC3,  0, 15, 0),
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun SOC_SINGLE("ALC Capture Noise Gate Switch", WM8510_NGATE,  3, 1, 0),
162*4882a593Smuzhiyun SOC_SINGLE("ALC Capture Noise Gate Threshold", WM8510_NGATE,  0, 7, 0),
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun SOC_SINGLE("Capture PGA ZC Switch", WM8510_INPPGA,  7, 1, 0),
165*4882a593Smuzhiyun SOC_SINGLE("Capture PGA Volume", WM8510_INPPGA,  0, 63, 0),
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun SOC_SINGLE("Speaker Playback ZC Switch", WM8510_SPKVOL,  7, 1, 0),
168*4882a593Smuzhiyun SOC_SINGLE("Speaker Playback Switch", WM8510_SPKVOL,  6, 1, 1),
169*4882a593Smuzhiyun SOC_SINGLE("Speaker Playback Volume", WM8510_SPKVOL,  0, 63, 0),
170*4882a593Smuzhiyun SOC_SINGLE("Speaker Boost", WM8510_OUTPUT, 2, 1, 0),
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun SOC_SINGLE("Capture Boost(+20dB)", WM8510_ADCBOOST,  8, 1, 0),
173*4882a593Smuzhiyun SOC_SINGLE("Mono Playback Switch", WM8510_MONOMIX, 6, 1, 1),
174*4882a593Smuzhiyun };
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun /* Speaker Output Mixer */
177*4882a593Smuzhiyun static const struct snd_kcontrol_new wm8510_speaker_mixer_controls[] = {
178*4882a593Smuzhiyun SOC_DAPM_SINGLE("Line Bypass Switch", WM8510_SPKMIX, 1, 1, 0),
179*4882a593Smuzhiyun SOC_DAPM_SINGLE("Aux Playback Switch", WM8510_SPKMIX, 5, 1, 0),
180*4882a593Smuzhiyun SOC_DAPM_SINGLE("PCM Playback Switch", WM8510_SPKMIX, 0, 1, 0),
181*4882a593Smuzhiyun };
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun /* Mono Output Mixer */
184*4882a593Smuzhiyun static const struct snd_kcontrol_new wm8510_mono_mixer_controls[] = {
185*4882a593Smuzhiyun SOC_DAPM_SINGLE("Line Bypass Switch", WM8510_MONOMIX, 1, 1, 0),
186*4882a593Smuzhiyun SOC_DAPM_SINGLE("Aux Playback Switch", WM8510_MONOMIX, 2, 1, 0),
187*4882a593Smuzhiyun SOC_DAPM_SINGLE("PCM Playback Switch", WM8510_MONOMIX, 0, 1, 0),
188*4882a593Smuzhiyun };
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun static const struct snd_kcontrol_new wm8510_boost_controls[] = {
191*4882a593Smuzhiyun SOC_DAPM_SINGLE("Mic PGA Switch", WM8510_INPPGA,  6, 1, 1),
192*4882a593Smuzhiyun SOC_DAPM_SINGLE("Aux Volume", WM8510_ADCBOOST, 0, 7, 0),
193*4882a593Smuzhiyun SOC_DAPM_SINGLE("Mic Volume", WM8510_ADCBOOST, 4, 7, 0),
194*4882a593Smuzhiyun };
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun static const struct snd_kcontrol_new wm8510_micpga_controls[] = {
197*4882a593Smuzhiyun SOC_DAPM_SINGLE("MICP Switch", WM8510_INPUT, 0, 1, 0),
198*4882a593Smuzhiyun SOC_DAPM_SINGLE("MICN Switch", WM8510_INPUT, 1, 1, 0),
199*4882a593Smuzhiyun SOC_DAPM_SINGLE("AUX Switch", WM8510_INPUT, 2, 1, 0),
200*4882a593Smuzhiyun };
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun static const struct snd_soc_dapm_widget wm8510_dapm_widgets[] = {
203*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Speaker Mixer", WM8510_POWER3, 2, 0,
204*4882a593Smuzhiyun 	&wm8510_speaker_mixer_controls[0],
205*4882a593Smuzhiyun 	ARRAY_SIZE(wm8510_speaker_mixer_controls)),
206*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Mono Mixer", WM8510_POWER3, 3, 0,
207*4882a593Smuzhiyun 	&wm8510_mono_mixer_controls[0],
208*4882a593Smuzhiyun 	ARRAY_SIZE(wm8510_mono_mixer_controls)),
209*4882a593Smuzhiyun SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM8510_POWER3, 0, 0),
210*4882a593Smuzhiyun SND_SOC_DAPM_ADC("ADC", "HiFi Capture", WM8510_POWER2, 0, 0),
211*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Aux Input", WM8510_POWER1, 6, 0, NULL, 0),
212*4882a593Smuzhiyun SND_SOC_DAPM_PGA("SpkN Out", WM8510_POWER3, 5, 0, NULL, 0),
213*4882a593Smuzhiyun SND_SOC_DAPM_PGA("SpkP Out", WM8510_POWER3, 6, 0, NULL, 0),
214*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Mono Out", WM8510_POWER3, 7, 0, NULL, 0),
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Mic PGA", WM8510_POWER2, 2, 0,
217*4882a593Smuzhiyun 		   &wm8510_micpga_controls[0],
218*4882a593Smuzhiyun 		   ARRAY_SIZE(wm8510_micpga_controls)),
219*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Boost Mixer", WM8510_POWER2, 4, 0,
220*4882a593Smuzhiyun 	&wm8510_boost_controls[0],
221*4882a593Smuzhiyun 	ARRAY_SIZE(wm8510_boost_controls)),
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun SND_SOC_DAPM_MICBIAS("Mic Bias", WM8510_POWER1, 4, 0),
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("MICN"),
226*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("MICP"),
227*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("AUX"),
228*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("MONOOUT"),
229*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPKOUTP"),
230*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPKOUTN"),
231*4882a593Smuzhiyun };
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun static const struct snd_soc_dapm_route wm8510_dapm_routes[] = {
234*4882a593Smuzhiyun 	/* Mono output mixer */
235*4882a593Smuzhiyun 	{"Mono Mixer", "PCM Playback Switch", "DAC"},
236*4882a593Smuzhiyun 	{"Mono Mixer", "Aux Playback Switch", "Aux Input"},
237*4882a593Smuzhiyun 	{"Mono Mixer", "Line Bypass Switch", "Boost Mixer"},
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun 	/* Speaker output mixer */
240*4882a593Smuzhiyun 	{"Speaker Mixer", "PCM Playback Switch", "DAC"},
241*4882a593Smuzhiyun 	{"Speaker Mixer", "Aux Playback Switch", "Aux Input"},
242*4882a593Smuzhiyun 	{"Speaker Mixer", "Line Bypass Switch", "Boost Mixer"},
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun 	/* Outputs */
245*4882a593Smuzhiyun 	{"Mono Out", NULL, "Mono Mixer"},
246*4882a593Smuzhiyun 	{"MONOOUT", NULL, "Mono Out"},
247*4882a593Smuzhiyun 	{"SpkN Out", NULL, "Speaker Mixer"},
248*4882a593Smuzhiyun 	{"SpkP Out", NULL, "Speaker Mixer"},
249*4882a593Smuzhiyun 	{"SPKOUTN", NULL, "SpkN Out"},
250*4882a593Smuzhiyun 	{"SPKOUTP", NULL, "SpkP Out"},
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun 	/* Microphone PGA */
253*4882a593Smuzhiyun 	{"Mic PGA", "MICN Switch", "MICN"},
254*4882a593Smuzhiyun 	{"Mic PGA", "MICP Switch", "MICP"},
255*4882a593Smuzhiyun 	{ "Mic PGA", "AUX Switch", "Aux Input" },
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun 	/* Boost Mixer */
258*4882a593Smuzhiyun 	{"Boost Mixer", "Mic PGA Switch", "Mic PGA"},
259*4882a593Smuzhiyun 	{"Boost Mixer", "Mic Volume", "MICP"},
260*4882a593Smuzhiyun 	{"Boost Mixer", "Aux Volume", "Aux Input"},
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun 	{"ADC", NULL, "Boost Mixer"},
263*4882a593Smuzhiyun };
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun struct pll_ {
266*4882a593Smuzhiyun 	unsigned int pre_div:4; /* prescale - 1 */
267*4882a593Smuzhiyun 	unsigned int n:4;
268*4882a593Smuzhiyun 	unsigned int k;
269*4882a593Smuzhiyun };
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun static struct pll_ pll_div;
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun /* The size in bits of the pll divide multiplied by 10
274*4882a593Smuzhiyun  * to allow rounding later */
275*4882a593Smuzhiyun #define FIXED_PLL_SIZE ((1 << 24) * 10)
276*4882a593Smuzhiyun 
pll_factors(unsigned int target,unsigned int source)277*4882a593Smuzhiyun static void pll_factors(unsigned int target, unsigned int source)
278*4882a593Smuzhiyun {
279*4882a593Smuzhiyun 	unsigned long long Kpart;
280*4882a593Smuzhiyun 	unsigned int K, Ndiv, Nmod;
281*4882a593Smuzhiyun 
282*4882a593Smuzhiyun 	Ndiv = target / source;
283*4882a593Smuzhiyun 	if (Ndiv < 6) {
284*4882a593Smuzhiyun 		source >>= 1;
285*4882a593Smuzhiyun 		pll_div.pre_div = 1;
286*4882a593Smuzhiyun 		Ndiv = target / source;
287*4882a593Smuzhiyun 	} else
288*4882a593Smuzhiyun 		pll_div.pre_div = 0;
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun 	if ((Ndiv < 6) || (Ndiv > 12))
291*4882a593Smuzhiyun 		printk(KERN_WARNING
292*4882a593Smuzhiyun 			"WM8510 N value %u outwith recommended range!d\n",
293*4882a593Smuzhiyun 			Ndiv);
294*4882a593Smuzhiyun 
295*4882a593Smuzhiyun 	pll_div.n = Ndiv;
296*4882a593Smuzhiyun 	Nmod = target % source;
297*4882a593Smuzhiyun 	Kpart = FIXED_PLL_SIZE * (long long)Nmod;
298*4882a593Smuzhiyun 
299*4882a593Smuzhiyun 	do_div(Kpart, source);
300*4882a593Smuzhiyun 
301*4882a593Smuzhiyun 	K = Kpart & 0xFFFFFFFF;
302*4882a593Smuzhiyun 
303*4882a593Smuzhiyun 	/* Check if we need to round */
304*4882a593Smuzhiyun 	if ((K % 10) >= 5)
305*4882a593Smuzhiyun 		K += 5;
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun 	/* Move down to proper range now rounding is done */
308*4882a593Smuzhiyun 	K /= 10;
309*4882a593Smuzhiyun 
310*4882a593Smuzhiyun 	pll_div.k = K;
311*4882a593Smuzhiyun }
312*4882a593Smuzhiyun 
wm8510_set_dai_pll(struct snd_soc_dai * codec_dai,int pll_id,int source,unsigned int freq_in,unsigned int freq_out)313*4882a593Smuzhiyun static int wm8510_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
314*4882a593Smuzhiyun 		int source, unsigned int freq_in, unsigned int freq_out)
315*4882a593Smuzhiyun {
316*4882a593Smuzhiyun 	struct snd_soc_component *component = codec_dai->component;
317*4882a593Smuzhiyun 	u16 reg;
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun 	if (freq_in == 0 || freq_out == 0) {
320*4882a593Smuzhiyun 		/* Clock CODEC directly from MCLK */
321*4882a593Smuzhiyun 		reg = snd_soc_component_read(component, WM8510_CLOCK);
322*4882a593Smuzhiyun 		snd_soc_component_write(component, WM8510_CLOCK, reg & 0x0ff);
323*4882a593Smuzhiyun 
324*4882a593Smuzhiyun 		/* Turn off PLL */
325*4882a593Smuzhiyun 		reg = snd_soc_component_read(component, WM8510_POWER1);
326*4882a593Smuzhiyun 		snd_soc_component_write(component, WM8510_POWER1, reg & 0x1df);
327*4882a593Smuzhiyun 		return 0;
328*4882a593Smuzhiyun 	}
329*4882a593Smuzhiyun 
330*4882a593Smuzhiyun 	pll_factors(freq_out*4, freq_in);
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun 	snd_soc_component_write(component, WM8510_PLLN, (pll_div.pre_div << 4) | pll_div.n);
333*4882a593Smuzhiyun 	snd_soc_component_write(component, WM8510_PLLK1, pll_div.k >> 18);
334*4882a593Smuzhiyun 	snd_soc_component_write(component, WM8510_PLLK2, (pll_div.k >> 9) & 0x1ff);
335*4882a593Smuzhiyun 	snd_soc_component_write(component, WM8510_PLLK3, pll_div.k & 0x1ff);
336*4882a593Smuzhiyun 	reg = snd_soc_component_read(component, WM8510_POWER1);
337*4882a593Smuzhiyun 	snd_soc_component_write(component, WM8510_POWER1, reg | 0x020);
338*4882a593Smuzhiyun 
339*4882a593Smuzhiyun 	/* Run CODEC from PLL instead of MCLK */
340*4882a593Smuzhiyun 	reg = snd_soc_component_read(component, WM8510_CLOCK);
341*4882a593Smuzhiyun 	snd_soc_component_write(component, WM8510_CLOCK, reg | 0x100);
342*4882a593Smuzhiyun 
343*4882a593Smuzhiyun 	return 0;
344*4882a593Smuzhiyun }
345*4882a593Smuzhiyun 
346*4882a593Smuzhiyun /*
347*4882a593Smuzhiyun  * Configure WM8510 clock dividers.
348*4882a593Smuzhiyun  */
wm8510_set_dai_clkdiv(struct snd_soc_dai * codec_dai,int div_id,int div)349*4882a593Smuzhiyun static int wm8510_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
350*4882a593Smuzhiyun 		int div_id, int div)
351*4882a593Smuzhiyun {
352*4882a593Smuzhiyun 	struct snd_soc_component *component = codec_dai->component;
353*4882a593Smuzhiyun 	u16 reg;
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun 	switch (div_id) {
356*4882a593Smuzhiyun 	case WM8510_OPCLKDIV:
357*4882a593Smuzhiyun 		reg = snd_soc_component_read(component, WM8510_GPIO) & 0x1cf;
358*4882a593Smuzhiyun 		snd_soc_component_write(component, WM8510_GPIO, reg | div);
359*4882a593Smuzhiyun 		break;
360*4882a593Smuzhiyun 	case WM8510_MCLKDIV:
361*4882a593Smuzhiyun 		reg = snd_soc_component_read(component, WM8510_CLOCK) & 0x11f;
362*4882a593Smuzhiyun 		snd_soc_component_write(component, WM8510_CLOCK, reg | div);
363*4882a593Smuzhiyun 		break;
364*4882a593Smuzhiyun 	case WM8510_ADCCLK:
365*4882a593Smuzhiyun 		reg = snd_soc_component_read(component, WM8510_ADC) & 0x1f7;
366*4882a593Smuzhiyun 		snd_soc_component_write(component, WM8510_ADC, reg | div);
367*4882a593Smuzhiyun 		break;
368*4882a593Smuzhiyun 	case WM8510_DACCLK:
369*4882a593Smuzhiyun 		reg = snd_soc_component_read(component, WM8510_DAC) & 0x1f7;
370*4882a593Smuzhiyun 		snd_soc_component_write(component, WM8510_DAC, reg | div);
371*4882a593Smuzhiyun 		break;
372*4882a593Smuzhiyun 	case WM8510_BCLKDIV:
373*4882a593Smuzhiyun 		reg = snd_soc_component_read(component, WM8510_CLOCK) & 0x1e3;
374*4882a593Smuzhiyun 		snd_soc_component_write(component, WM8510_CLOCK, reg | div);
375*4882a593Smuzhiyun 		break;
376*4882a593Smuzhiyun 	default:
377*4882a593Smuzhiyun 		return -EINVAL;
378*4882a593Smuzhiyun 	}
379*4882a593Smuzhiyun 
380*4882a593Smuzhiyun 	return 0;
381*4882a593Smuzhiyun }
382*4882a593Smuzhiyun 
wm8510_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)383*4882a593Smuzhiyun static int wm8510_set_dai_fmt(struct snd_soc_dai *codec_dai,
384*4882a593Smuzhiyun 		unsigned int fmt)
385*4882a593Smuzhiyun {
386*4882a593Smuzhiyun 	struct snd_soc_component *component = codec_dai->component;
387*4882a593Smuzhiyun 	u16 iface = 0;
388*4882a593Smuzhiyun 	u16 clk = snd_soc_component_read(component, WM8510_CLOCK) & 0x1fe;
389*4882a593Smuzhiyun 
390*4882a593Smuzhiyun 	/* set master/slave audio interface */
391*4882a593Smuzhiyun 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
392*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_CBM_CFM:
393*4882a593Smuzhiyun 		clk |= 0x0001;
394*4882a593Smuzhiyun 		break;
395*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_CBS_CFS:
396*4882a593Smuzhiyun 		break;
397*4882a593Smuzhiyun 	default:
398*4882a593Smuzhiyun 		return -EINVAL;
399*4882a593Smuzhiyun 	}
400*4882a593Smuzhiyun 
401*4882a593Smuzhiyun 	/* interface format */
402*4882a593Smuzhiyun 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
403*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_I2S:
404*4882a593Smuzhiyun 		iface |= 0x0010;
405*4882a593Smuzhiyun 		break;
406*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_RIGHT_J:
407*4882a593Smuzhiyun 		break;
408*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_LEFT_J:
409*4882a593Smuzhiyun 		iface |= 0x0008;
410*4882a593Smuzhiyun 		break;
411*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_DSP_A:
412*4882a593Smuzhiyun 		iface |= 0x00018;
413*4882a593Smuzhiyun 		break;
414*4882a593Smuzhiyun 	default:
415*4882a593Smuzhiyun 		return -EINVAL;
416*4882a593Smuzhiyun 	}
417*4882a593Smuzhiyun 
418*4882a593Smuzhiyun 	/* clock inversion */
419*4882a593Smuzhiyun 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
420*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_NB_NF:
421*4882a593Smuzhiyun 		break;
422*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_IB_IF:
423*4882a593Smuzhiyun 		iface |= 0x0180;
424*4882a593Smuzhiyun 		break;
425*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_IB_NF:
426*4882a593Smuzhiyun 		iface |= 0x0100;
427*4882a593Smuzhiyun 		break;
428*4882a593Smuzhiyun 	case SND_SOC_DAIFMT_NB_IF:
429*4882a593Smuzhiyun 		iface |= 0x0080;
430*4882a593Smuzhiyun 		break;
431*4882a593Smuzhiyun 	default:
432*4882a593Smuzhiyun 		return -EINVAL;
433*4882a593Smuzhiyun 	}
434*4882a593Smuzhiyun 
435*4882a593Smuzhiyun 	snd_soc_component_write(component, WM8510_IFACE, iface);
436*4882a593Smuzhiyun 	snd_soc_component_write(component, WM8510_CLOCK, clk);
437*4882a593Smuzhiyun 	return 0;
438*4882a593Smuzhiyun }
439*4882a593Smuzhiyun 
wm8510_pcm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)440*4882a593Smuzhiyun static int wm8510_pcm_hw_params(struct snd_pcm_substream *substream,
441*4882a593Smuzhiyun 				struct snd_pcm_hw_params *params,
442*4882a593Smuzhiyun 				struct snd_soc_dai *dai)
443*4882a593Smuzhiyun {
444*4882a593Smuzhiyun 	struct snd_soc_component *component = dai->component;
445*4882a593Smuzhiyun 	u16 iface = snd_soc_component_read(component, WM8510_IFACE) & 0x19f;
446*4882a593Smuzhiyun 	u16 adn = snd_soc_component_read(component, WM8510_ADD) & 0x1f1;
447*4882a593Smuzhiyun 
448*4882a593Smuzhiyun 	/* bit size */
449*4882a593Smuzhiyun 	switch (params_width(params)) {
450*4882a593Smuzhiyun 	case 16:
451*4882a593Smuzhiyun 		break;
452*4882a593Smuzhiyun 	case 20:
453*4882a593Smuzhiyun 		iface |= 0x0020;
454*4882a593Smuzhiyun 		break;
455*4882a593Smuzhiyun 	case 24:
456*4882a593Smuzhiyun 		iface |= 0x0040;
457*4882a593Smuzhiyun 		break;
458*4882a593Smuzhiyun 	case 32:
459*4882a593Smuzhiyun 		iface |= 0x0060;
460*4882a593Smuzhiyun 		break;
461*4882a593Smuzhiyun 	}
462*4882a593Smuzhiyun 
463*4882a593Smuzhiyun 	/* filter coefficient */
464*4882a593Smuzhiyun 	switch (params_rate(params)) {
465*4882a593Smuzhiyun 	case 8000:
466*4882a593Smuzhiyun 		adn |= 0x5 << 1;
467*4882a593Smuzhiyun 		break;
468*4882a593Smuzhiyun 	case 11025:
469*4882a593Smuzhiyun 		adn |= 0x4 << 1;
470*4882a593Smuzhiyun 		break;
471*4882a593Smuzhiyun 	case 16000:
472*4882a593Smuzhiyun 		adn |= 0x3 << 1;
473*4882a593Smuzhiyun 		break;
474*4882a593Smuzhiyun 	case 22050:
475*4882a593Smuzhiyun 		adn |= 0x2 << 1;
476*4882a593Smuzhiyun 		break;
477*4882a593Smuzhiyun 	case 32000:
478*4882a593Smuzhiyun 		adn |= 0x1 << 1;
479*4882a593Smuzhiyun 		break;
480*4882a593Smuzhiyun 	case 44100:
481*4882a593Smuzhiyun 	case 48000:
482*4882a593Smuzhiyun 		break;
483*4882a593Smuzhiyun 	}
484*4882a593Smuzhiyun 
485*4882a593Smuzhiyun 	snd_soc_component_write(component, WM8510_IFACE, iface);
486*4882a593Smuzhiyun 	snd_soc_component_write(component, WM8510_ADD, adn);
487*4882a593Smuzhiyun 	return 0;
488*4882a593Smuzhiyun }
489*4882a593Smuzhiyun 
wm8510_mute(struct snd_soc_dai * dai,int mute,int direction)490*4882a593Smuzhiyun static int wm8510_mute(struct snd_soc_dai *dai, int mute, int direction)
491*4882a593Smuzhiyun {
492*4882a593Smuzhiyun 	struct snd_soc_component *component = dai->component;
493*4882a593Smuzhiyun 	u16 mute_reg = snd_soc_component_read(component, WM8510_DAC) & 0xffbf;
494*4882a593Smuzhiyun 
495*4882a593Smuzhiyun 	if (mute)
496*4882a593Smuzhiyun 		snd_soc_component_write(component, WM8510_DAC, mute_reg | 0x40);
497*4882a593Smuzhiyun 	else
498*4882a593Smuzhiyun 		snd_soc_component_write(component, WM8510_DAC, mute_reg);
499*4882a593Smuzhiyun 	return 0;
500*4882a593Smuzhiyun }
501*4882a593Smuzhiyun 
502*4882a593Smuzhiyun /* liam need to make this lower power with dapm */
wm8510_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)503*4882a593Smuzhiyun static int wm8510_set_bias_level(struct snd_soc_component *component,
504*4882a593Smuzhiyun 	enum snd_soc_bias_level level)
505*4882a593Smuzhiyun {
506*4882a593Smuzhiyun 	struct wm8510_priv *wm8510 = snd_soc_component_get_drvdata(component);
507*4882a593Smuzhiyun 	u16 power1 = snd_soc_component_read(component, WM8510_POWER1) & ~0x3;
508*4882a593Smuzhiyun 
509*4882a593Smuzhiyun 	switch (level) {
510*4882a593Smuzhiyun 	case SND_SOC_BIAS_ON:
511*4882a593Smuzhiyun 	case SND_SOC_BIAS_PREPARE:
512*4882a593Smuzhiyun 		power1 |= 0x1;  /* VMID 50k */
513*4882a593Smuzhiyun 		snd_soc_component_write(component, WM8510_POWER1, power1);
514*4882a593Smuzhiyun 		break;
515*4882a593Smuzhiyun 
516*4882a593Smuzhiyun 	case SND_SOC_BIAS_STANDBY:
517*4882a593Smuzhiyun 		power1 |= WM8510_POWER1_BIASEN | WM8510_POWER1_BUFIOEN;
518*4882a593Smuzhiyun 
519*4882a593Smuzhiyun 		if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
520*4882a593Smuzhiyun 			regcache_sync(wm8510->regmap);
521*4882a593Smuzhiyun 
522*4882a593Smuzhiyun 			/* Initial cap charge at VMID 5k */
523*4882a593Smuzhiyun 			snd_soc_component_write(component, WM8510_POWER1, power1 | 0x3);
524*4882a593Smuzhiyun 			mdelay(100);
525*4882a593Smuzhiyun 		}
526*4882a593Smuzhiyun 
527*4882a593Smuzhiyun 		power1 |= 0x2;  /* VMID 500k */
528*4882a593Smuzhiyun 		snd_soc_component_write(component, WM8510_POWER1, power1);
529*4882a593Smuzhiyun 		break;
530*4882a593Smuzhiyun 
531*4882a593Smuzhiyun 	case SND_SOC_BIAS_OFF:
532*4882a593Smuzhiyun 		snd_soc_component_write(component, WM8510_POWER1, 0);
533*4882a593Smuzhiyun 		snd_soc_component_write(component, WM8510_POWER2, 0);
534*4882a593Smuzhiyun 		snd_soc_component_write(component, WM8510_POWER3, 0);
535*4882a593Smuzhiyun 		break;
536*4882a593Smuzhiyun 	}
537*4882a593Smuzhiyun 
538*4882a593Smuzhiyun 	return 0;
539*4882a593Smuzhiyun }
540*4882a593Smuzhiyun 
541*4882a593Smuzhiyun #define WM8510_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
542*4882a593Smuzhiyun 		SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
543*4882a593Smuzhiyun 		SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
544*4882a593Smuzhiyun 
545*4882a593Smuzhiyun #define WM8510_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
546*4882a593Smuzhiyun 	SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
547*4882a593Smuzhiyun 
548*4882a593Smuzhiyun static const struct snd_soc_dai_ops wm8510_dai_ops = {
549*4882a593Smuzhiyun 	.hw_params	= wm8510_pcm_hw_params,
550*4882a593Smuzhiyun 	.mute_stream	= wm8510_mute,
551*4882a593Smuzhiyun 	.set_fmt	= wm8510_set_dai_fmt,
552*4882a593Smuzhiyun 	.set_clkdiv	= wm8510_set_dai_clkdiv,
553*4882a593Smuzhiyun 	.set_pll	= wm8510_set_dai_pll,
554*4882a593Smuzhiyun 	.no_capture_mute = 1,
555*4882a593Smuzhiyun };
556*4882a593Smuzhiyun 
557*4882a593Smuzhiyun static struct snd_soc_dai_driver wm8510_dai = {
558*4882a593Smuzhiyun 	.name = "wm8510-hifi",
559*4882a593Smuzhiyun 	.playback = {
560*4882a593Smuzhiyun 		.stream_name = "Playback",
561*4882a593Smuzhiyun 		.channels_min = 2,
562*4882a593Smuzhiyun 		.channels_max = 2,
563*4882a593Smuzhiyun 		.rates = WM8510_RATES,
564*4882a593Smuzhiyun 		.formats = WM8510_FORMATS,},
565*4882a593Smuzhiyun 	.capture = {
566*4882a593Smuzhiyun 		.stream_name = "Capture",
567*4882a593Smuzhiyun 		.channels_min = 2,
568*4882a593Smuzhiyun 		.channels_max = 2,
569*4882a593Smuzhiyun 		.rates = WM8510_RATES,
570*4882a593Smuzhiyun 		.formats = WM8510_FORMATS,},
571*4882a593Smuzhiyun 	.ops = &wm8510_dai_ops,
572*4882a593Smuzhiyun 	.symmetric_rates = 1,
573*4882a593Smuzhiyun };
574*4882a593Smuzhiyun 
wm8510_probe(struct snd_soc_component * component)575*4882a593Smuzhiyun static int wm8510_probe(struct snd_soc_component *component)
576*4882a593Smuzhiyun {
577*4882a593Smuzhiyun 	wm8510_reset(component);
578*4882a593Smuzhiyun 
579*4882a593Smuzhiyun 	return 0;
580*4882a593Smuzhiyun }
581*4882a593Smuzhiyun 
582*4882a593Smuzhiyun static const struct snd_soc_component_driver soc_component_dev_wm8510 = {
583*4882a593Smuzhiyun 	.probe			= wm8510_probe,
584*4882a593Smuzhiyun 	.set_bias_level		= wm8510_set_bias_level,
585*4882a593Smuzhiyun 	.controls		= wm8510_snd_controls,
586*4882a593Smuzhiyun 	.num_controls		= ARRAY_SIZE(wm8510_snd_controls),
587*4882a593Smuzhiyun 	.dapm_widgets		= wm8510_dapm_widgets,
588*4882a593Smuzhiyun 	.num_dapm_widgets	= ARRAY_SIZE(wm8510_dapm_widgets),
589*4882a593Smuzhiyun 	.dapm_routes		= wm8510_dapm_routes,
590*4882a593Smuzhiyun 	.num_dapm_routes	= ARRAY_SIZE(wm8510_dapm_routes),
591*4882a593Smuzhiyun 	.suspend_bias_off	= 1,
592*4882a593Smuzhiyun 	.idle_bias_on		= 1,
593*4882a593Smuzhiyun 	.use_pmdown_time	= 1,
594*4882a593Smuzhiyun 	.endianness		= 1,
595*4882a593Smuzhiyun 	.non_legacy_dai_naming	= 1,
596*4882a593Smuzhiyun };
597*4882a593Smuzhiyun 
598*4882a593Smuzhiyun static const struct of_device_id wm8510_of_match[] = {
599*4882a593Smuzhiyun 	{ .compatible = "wlf,wm8510" },
600*4882a593Smuzhiyun 	{ },
601*4882a593Smuzhiyun };
602*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, wm8510_of_match);
603*4882a593Smuzhiyun 
604*4882a593Smuzhiyun static const struct regmap_config wm8510_regmap = {
605*4882a593Smuzhiyun 	.reg_bits = 7,
606*4882a593Smuzhiyun 	.val_bits = 9,
607*4882a593Smuzhiyun 	.max_register = WM8510_MONOMIX,
608*4882a593Smuzhiyun 
609*4882a593Smuzhiyun 	.reg_defaults = wm8510_reg_defaults,
610*4882a593Smuzhiyun 	.num_reg_defaults = ARRAY_SIZE(wm8510_reg_defaults),
611*4882a593Smuzhiyun 	.cache_type = REGCACHE_RBTREE,
612*4882a593Smuzhiyun 
613*4882a593Smuzhiyun 	.volatile_reg = wm8510_volatile,
614*4882a593Smuzhiyun };
615*4882a593Smuzhiyun 
616*4882a593Smuzhiyun #if defined(CONFIG_SPI_MASTER)
wm8510_spi_probe(struct spi_device * spi)617*4882a593Smuzhiyun static int wm8510_spi_probe(struct spi_device *spi)
618*4882a593Smuzhiyun {
619*4882a593Smuzhiyun 	struct wm8510_priv *wm8510;
620*4882a593Smuzhiyun 	int ret;
621*4882a593Smuzhiyun 
622*4882a593Smuzhiyun 	wm8510 = devm_kzalloc(&spi->dev, sizeof(struct wm8510_priv),
623*4882a593Smuzhiyun 			      GFP_KERNEL);
624*4882a593Smuzhiyun 	if (wm8510 == NULL)
625*4882a593Smuzhiyun 		return -ENOMEM;
626*4882a593Smuzhiyun 
627*4882a593Smuzhiyun 	wm8510->regmap = devm_regmap_init_spi(spi, &wm8510_regmap);
628*4882a593Smuzhiyun 	if (IS_ERR(wm8510->regmap))
629*4882a593Smuzhiyun 		return PTR_ERR(wm8510->regmap);
630*4882a593Smuzhiyun 
631*4882a593Smuzhiyun 	spi_set_drvdata(spi, wm8510);
632*4882a593Smuzhiyun 
633*4882a593Smuzhiyun 	ret = devm_snd_soc_register_component(&spi->dev,
634*4882a593Smuzhiyun 			&soc_component_dev_wm8510, &wm8510_dai, 1);
635*4882a593Smuzhiyun 
636*4882a593Smuzhiyun 	return ret;
637*4882a593Smuzhiyun }
638*4882a593Smuzhiyun 
639*4882a593Smuzhiyun static struct spi_driver wm8510_spi_driver = {
640*4882a593Smuzhiyun 	.driver = {
641*4882a593Smuzhiyun 		.name	= "wm8510",
642*4882a593Smuzhiyun 		.of_match_table = wm8510_of_match,
643*4882a593Smuzhiyun 	},
644*4882a593Smuzhiyun 	.probe		= wm8510_spi_probe,
645*4882a593Smuzhiyun };
646*4882a593Smuzhiyun #endif /* CONFIG_SPI_MASTER */
647*4882a593Smuzhiyun 
648*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_I2C)
wm8510_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)649*4882a593Smuzhiyun static int wm8510_i2c_probe(struct i2c_client *i2c,
650*4882a593Smuzhiyun 			    const struct i2c_device_id *id)
651*4882a593Smuzhiyun {
652*4882a593Smuzhiyun 	struct wm8510_priv *wm8510;
653*4882a593Smuzhiyun 	int ret;
654*4882a593Smuzhiyun 
655*4882a593Smuzhiyun 	wm8510 = devm_kzalloc(&i2c->dev, sizeof(struct wm8510_priv),
656*4882a593Smuzhiyun 			      GFP_KERNEL);
657*4882a593Smuzhiyun 	if (wm8510 == NULL)
658*4882a593Smuzhiyun 		return -ENOMEM;
659*4882a593Smuzhiyun 
660*4882a593Smuzhiyun 	wm8510->regmap = devm_regmap_init_i2c(i2c, &wm8510_regmap);
661*4882a593Smuzhiyun 	if (IS_ERR(wm8510->regmap))
662*4882a593Smuzhiyun 		return PTR_ERR(wm8510->regmap);
663*4882a593Smuzhiyun 
664*4882a593Smuzhiyun 	i2c_set_clientdata(i2c, wm8510);
665*4882a593Smuzhiyun 
666*4882a593Smuzhiyun 	ret = devm_snd_soc_register_component(&i2c->dev,
667*4882a593Smuzhiyun 			&soc_component_dev_wm8510, &wm8510_dai, 1);
668*4882a593Smuzhiyun 
669*4882a593Smuzhiyun 	return ret;
670*4882a593Smuzhiyun }
671*4882a593Smuzhiyun 
672*4882a593Smuzhiyun static const struct i2c_device_id wm8510_i2c_id[] = {
673*4882a593Smuzhiyun 	{ "wm8510", 0 },
674*4882a593Smuzhiyun 	{ }
675*4882a593Smuzhiyun };
676*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, wm8510_i2c_id);
677*4882a593Smuzhiyun 
678*4882a593Smuzhiyun static struct i2c_driver wm8510_i2c_driver = {
679*4882a593Smuzhiyun 	.driver = {
680*4882a593Smuzhiyun 		.name = "wm8510",
681*4882a593Smuzhiyun 		.of_match_table = wm8510_of_match,
682*4882a593Smuzhiyun 	},
683*4882a593Smuzhiyun 	.probe =    wm8510_i2c_probe,
684*4882a593Smuzhiyun 	.id_table = wm8510_i2c_id,
685*4882a593Smuzhiyun };
686*4882a593Smuzhiyun #endif
687*4882a593Smuzhiyun 
wm8510_modinit(void)688*4882a593Smuzhiyun static int __init wm8510_modinit(void)
689*4882a593Smuzhiyun {
690*4882a593Smuzhiyun 	int ret = 0;
691*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_I2C)
692*4882a593Smuzhiyun 	ret = i2c_add_driver(&wm8510_i2c_driver);
693*4882a593Smuzhiyun 	if (ret != 0) {
694*4882a593Smuzhiyun 		printk(KERN_ERR "Failed to register WM8510 I2C driver: %d\n",
695*4882a593Smuzhiyun 		       ret);
696*4882a593Smuzhiyun 	}
697*4882a593Smuzhiyun #endif
698*4882a593Smuzhiyun #if defined(CONFIG_SPI_MASTER)
699*4882a593Smuzhiyun 	ret = spi_register_driver(&wm8510_spi_driver);
700*4882a593Smuzhiyun 	if (ret != 0) {
701*4882a593Smuzhiyun 		printk(KERN_ERR "Failed to register WM8510 SPI driver: %d\n",
702*4882a593Smuzhiyun 		       ret);
703*4882a593Smuzhiyun 	}
704*4882a593Smuzhiyun #endif
705*4882a593Smuzhiyun 	return ret;
706*4882a593Smuzhiyun }
707*4882a593Smuzhiyun module_init(wm8510_modinit);
708*4882a593Smuzhiyun 
wm8510_exit(void)709*4882a593Smuzhiyun static void __exit wm8510_exit(void)
710*4882a593Smuzhiyun {
711*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_I2C)
712*4882a593Smuzhiyun 	i2c_del_driver(&wm8510_i2c_driver);
713*4882a593Smuzhiyun #endif
714*4882a593Smuzhiyun #if defined(CONFIG_SPI_MASTER)
715*4882a593Smuzhiyun 	spi_unregister_driver(&wm8510_spi_driver);
716*4882a593Smuzhiyun #endif
717*4882a593Smuzhiyun }
718*4882a593Smuzhiyun module_exit(wm8510_exit);
719*4882a593Smuzhiyun 
720*4882a593Smuzhiyun MODULE_DESCRIPTION("ASoC WM8510 driver");
721*4882a593Smuzhiyun MODULE_AUTHOR("Liam Girdwood");
722*4882a593Smuzhiyun MODULE_LICENSE("GPL");
723