31 struct pll_div {  struct
48 static struct pll_div rk3368_pll_rates[] = {  argument
113 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2);
114 static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2);
116 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2);
117 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6);
129 struct pll_div *rkclk_get_pll_config(ulong freq_hz)  in rkclk_get_pll_config()
141 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)  in pll_para_config()
143 	struct pll_div *best_div = NULL;  in pll_para_config()
250 			 const struct pll_div *div)  in rkclk_set_pll()
420 	const struct pll_div *dpll_cfg = NULL;  in rk3368_ddr_set_clk()
424 	static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1);  in rk3368_ddr_set_clk()
425 	static const struct pll_div dpll_1332 =	PLL_DIVISORS(1332 * MHz, 2, 1);  in rk3368_ddr_set_clk()
426 	static const struct pll_div dpll_1600 =	PLL_DIVISORS(1600 * MHz, 3, 2);  in rk3368_ddr_set_clk()
770 	struct pll_div npll_config = {0};  in rk3368_vop_set_clk()
872 	struct pll_div pll_config = {0};  in rk3368_armclk_set_clk()
874 	u32 pll_div, pll_id, con_id;  in rk3368_armclk_set_clk()  local
889 	ret = pll_para_config(hz, &pll_config, &pll_div);  in rk3368_armclk_set_clk()
1000 	struct pll_div pll_config = {0};  in rk3368_clk_set_rate()
1001 	u32 pll_div;  in rk3368_clk_set_rate()  local
1010 		ret = pll_para_config(rate, &pll_config, &pll_div);  in rk3368_clk_set_rate()