1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * wm8974.c -- WM8974 ALSA Soc Audio driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2006-2009 Wolfson Microelectronics PLC.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Liam Girdwood <Liam.Girdwood@wolfsonmicro.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/clk.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/init.h>
14*4882a593Smuzhiyun #include <linux/delay.h>
15*4882a593Smuzhiyun #include <linux/pm.h>
16*4882a593Smuzhiyun #include <linux/i2c.h>
17*4882a593Smuzhiyun #include <linux/regmap.h>
18*4882a593Smuzhiyun #include <linux/slab.h>
19*4882a593Smuzhiyun #include <sound/core.h>
20*4882a593Smuzhiyun #include <sound/pcm.h>
21*4882a593Smuzhiyun #include <sound/pcm_params.h>
22*4882a593Smuzhiyun #include <sound/soc.h>
23*4882a593Smuzhiyun #include <sound/initval.h>
24*4882a593Smuzhiyun #include <sound/tlv.h>
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #include "wm8974.h"
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun struct wm8974_priv {
29*4882a593Smuzhiyun unsigned int mclk;
30*4882a593Smuzhiyun unsigned int fs;
31*4882a593Smuzhiyun struct clk *mclk_in;
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun static const struct reg_default wm8974_reg_defaults[] = {
35*4882a593Smuzhiyun { 0, 0x0000 }, { 1, 0x0000 }, { 2, 0x0000 }, { 3, 0x0000 },
36*4882a593Smuzhiyun { 4, 0x0050 }, { 5, 0x0000 }, { 6, 0x0140 }, { 7, 0x0000 },
37*4882a593Smuzhiyun { 8, 0x0000 }, { 9, 0x0000 }, { 10, 0x0000 }, { 11, 0x00ff },
38*4882a593Smuzhiyun { 12, 0x0000 }, { 13, 0x0000 }, { 14, 0x0100 }, { 15, 0x00ff },
39*4882a593Smuzhiyun { 16, 0x0000 }, { 17, 0x0000 }, { 18, 0x012c }, { 19, 0x002c },
40*4882a593Smuzhiyun { 20, 0x002c }, { 21, 0x002c }, { 22, 0x002c }, { 23, 0x0000 },
41*4882a593Smuzhiyun { 24, 0x0032 }, { 25, 0x0000 }, { 26, 0x0000 }, { 27, 0x0000 },
42*4882a593Smuzhiyun { 28, 0x0000 }, { 29, 0x0000 }, { 30, 0x0000 }, { 31, 0x0000 },
43*4882a593Smuzhiyun { 32, 0x0038 }, { 33, 0x000b }, { 34, 0x0032 }, { 35, 0x0000 },
44*4882a593Smuzhiyun { 36, 0x0008 }, { 37, 0x000c }, { 38, 0x0093 }, { 39, 0x00e9 },
45*4882a593Smuzhiyun { 40, 0x0000 }, { 41, 0x0000 }, { 42, 0x0000 }, { 43, 0x0000 },
46*4882a593Smuzhiyun { 44, 0x0003 }, { 45, 0x0010 }, { 46, 0x0000 }, { 47, 0x0000 },
47*4882a593Smuzhiyun { 48, 0x0000 }, { 49, 0x0002 }, { 50, 0x0000 }, { 51, 0x0000 },
48*4882a593Smuzhiyun { 52, 0x0000 }, { 53, 0x0000 }, { 54, 0x0039 }, { 55, 0x0000 },
49*4882a593Smuzhiyun { 56, 0x0000 },
50*4882a593Smuzhiyun };
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun #define WM8974_POWER1_BIASEN 0x08
53*4882a593Smuzhiyun #define WM8974_POWER1_BUFIOEN 0x04
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun #define wm8974_reset(c) snd_soc_component_write(c, WM8974_RESET, 0)
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun static const char *wm8974_companding[] = {"Off", "NC", "u-law", "A-law" };
58*4882a593Smuzhiyun static const char *wm8974_deemp[] = {"None", "32kHz", "44.1kHz", "48kHz" };
59*4882a593Smuzhiyun static const char *wm8974_eqmode[] = {"Capture", "Playback" };
60*4882a593Smuzhiyun static const char *wm8974_bw[] = {"Narrow", "Wide" };
61*4882a593Smuzhiyun static const char *wm8974_eq1[] = {"80Hz", "105Hz", "135Hz", "175Hz" };
62*4882a593Smuzhiyun static const char *wm8974_eq2[] = {"230Hz", "300Hz", "385Hz", "500Hz" };
63*4882a593Smuzhiyun static const char *wm8974_eq3[] = {"650Hz", "850Hz", "1.1kHz", "1.4kHz" };
64*4882a593Smuzhiyun static const char *wm8974_eq4[] = {"1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz" };
65*4882a593Smuzhiyun static const char *wm8974_eq5[] = {"5.3kHz", "6.9kHz", "9kHz", "11.7kHz" };
66*4882a593Smuzhiyun static const char *wm8974_alc[] = {"ALC", "Limiter" };
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun static const struct soc_enum wm8974_enum[] = {
69*4882a593Smuzhiyun SOC_ENUM_SINGLE(WM8974_COMP, 1, 4, wm8974_companding), /* adc */
70*4882a593Smuzhiyun SOC_ENUM_SINGLE(WM8974_COMP, 3, 4, wm8974_companding), /* dac */
71*4882a593Smuzhiyun SOC_ENUM_SINGLE(WM8974_DAC, 4, 4, wm8974_deemp),
72*4882a593Smuzhiyun SOC_ENUM_SINGLE(WM8974_EQ1, 8, 2, wm8974_eqmode),
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun SOC_ENUM_SINGLE(WM8974_EQ1, 5, 4, wm8974_eq1),
75*4882a593Smuzhiyun SOC_ENUM_SINGLE(WM8974_EQ2, 8, 2, wm8974_bw),
76*4882a593Smuzhiyun SOC_ENUM_SINGLE(WM8974_EQ2, 5, 4, wm8974_eq2),
77*4882a593Smuzhiyun SOC_ENUM_SINGLE(WM8974_EQ3, 8, 2, wm8974_bw),
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun SOC_ENUM_SINGLE(WM8974_EQ3, 5, 4, wm8974_eq3),
80*4882a593Smuzhiyun SOC_ENUM_SINGLE(WM8974_EQ4, 8, 2, wm8974_bw),
81*4882a593Smuzhiyun SOC_ENUM_SINGLE(WM8974_EQ4, 5, 4, wm8974_eq4),
82*4882a593Smuzhiyun SOC_ENUM_SINGLE(WM8974_EQ5, 8, 2, wm8974_bw),
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun SOC_ENUM_SINGLE(WM8974_EQ5, 5, 4, wm8974_eq5),
85*4882a593Smuzhiyun SOC_ENUM_SINGLE(WM8974_ALC3, 8, 2, wm8974_alc),
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun static const char *wm8974_auxmode_text[] = { "Buffer", "Mixer" };
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun static SOC_ENUM_SINGLE_DECL(wm8974_auxmode,
91*4882a593Smuzhiyun WM8974_INPUT, 3, wm8974_auxmode_text);
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
94*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
95*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1200, 75, 0);
96*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(spk_tlv, -5700, 100, 0);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun static const struct snd_kcontrol_new wm8974_snd_controls[] = {
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun SOC_SINGLE("Digital Loopback Switch", WM8974_COMP, 0, 1, 0),
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun SOC_ENUM("DAC Companding", wm8974_enum[1]),
103*4882a593Smuzhiyun SOC_ENUM("ADC Companding", wm8974_enum[0]),
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun SOC_ENUM("Playback De-emphasis", wm8974_enum[2]),
106*4882a593Smuzhiyun SOC_SINGLE("DAC Inversion Switch", WM8974_DAC, 0, 1, 0),
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun SOC_SINGLE_TLV("PCM Volume", WM8974_DACVOL, 0, 255, 0, digital_tlv),
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun SOC_SINGLE("High Pass Filter Switch", WM8974_ADC, 8, 1, 0),
111*4882a593Smuzhiyun SOC_SINGLE("High Pass Cut Off", WM8974_ADC, 4, 7, 0),
112*4882a593Smuzhiyun SOC_SINGLE("ADC Inversion Switch", WM8974_ADC, 0, 1, 0),
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun SOC_SINGLE_TLV("Capture Volume", WM8974_ADCVOL, 0, 255, 0, digital_tlv),
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun SOC_ENUM("Equaliser Function", wm8974_enum[3]),
117*4882a593Smuzhiyun SOC_ENUM("EQ1 Cut Off", wm8974_enum[4]),
118*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ1 Volume", WM8974_EQ1, 0, 24, 1, eq_tlv),
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun SOC_ENUM("Equaliser EQ2 Bandwidth", wm8974_enum[5]),
121*4882a593Smuzhiyun SOC_ENUM("EQ2 Cut Off", wm8974_enum[6]),
122*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ2 Volume", WM8974_EQ2, 0, 24, 1, eq_tlv),
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun SOC_ENUM("Equaliser EQ3 Bandwidth", wm8974_enum[7]),
125*4882a593Smuzhiyun SOC_ENUM("EQ3 Cut Off", wm8974_enum[8]),
126*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ3 Volume", WM8974_EQ3, 0, 24, 1, eq_tlv),
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun SOC_ENUM("Equaliser EQ4 Bandwidth", wm8974_enum[9]),
129*4882a593Smuzhiyun SOC_ENUM("EQ4 Cut Off", wm8974_enum[10]),
130*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ4 Volume", WM8974_EQ4, 0, 24, 1, eq_tlv),
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun SOC_ENUM("Equaliser EQ5 Bandwidth", wm8974_enum[11]),
133*4882a593Smuzhiyun SOC_ENUM("EQ5 Cut Off", wm8974_enum[12]),
134*4882a593Smuzhiyun SOC_SINGLE_TLV("EQ5 Volume", WM8974_EQ5, 0, 24, 1, eq_tlv),
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun SOC_SINGLE("DAC Playback Limiter Switch", WM8974_DACLIM1, 8, 1, 0),
137*4882a593Smuzhiyun SOC_SINGLE("DAC Playback Limiter Decay", WM8974_DACLIM1, 4, 15, 0),
138*4882a593Smuzhiyun SOC_SINGLE("DAC Playback Limiter Attack", WM8974_DACLIM1, 0, 15, 0),
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun SOC_SINGLE("DAC Playback Limiter Threshold", WM8974_DACLIM2, 4, 7, 0),
141*4882a593Smuzhiyun SOC_SINGLE("DAC Playback Limiter Boost", WM8974_DACLIM2, 0, 15, 0),
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun SOC_SINGLE("ALC Enable Switch", WM8974_ALC1, 8, 1, 0),
144*4882a593Smuzhiyun SOC_SINGLE("ALC Capture Max Gain", WM8974_ALC1, 3, 7, 0),
145*4882a593Smuzhiyun SOC_SINGLE("ALC Capture Min Gain", WM8974_ALC1, 0, 7, 0),
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun SOC_SINGLE("ALC Capture ZC Switch", WM8974_ALC2, 8, 1, 0),
148*4882a593Smuzhiyun SOC_SINGLE("ALC Capture Hold", WM8974_ALC2, 4, 7, 0),
149*4882a593Smuzhiyun SOC_SINGLE("ALC Capture Target", WM8974_ALC2, 0, 15, 0),
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun SOC_ENUM("ALC Capture Mode", wm8974_enum[13]),
152*4882a593Smuzhiyun SOC_SINGLE("ALC Capture Decay", WM8974_ALC3, 4, 15, 0),
153*4882a593Smuzhiyun SOC_SINGLE("ALC Capture Attack", WM8974_ALC3, 0, 15, 0),
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun SOC_SINGLE("ALC Capture Noise Gate Switch", WM8974_NGATE, 3, 1, 0),
156*4882a593Smuzhiyun SOC_SINGLE("ALC Capture Noise Gate Threshold", WM8974_NGATE, 0, 7, 0),
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun SOC_SINGLE("Capture PGA ZC Switch", WM8974_INPPGA, 7, 1, 0),
159*4882a593Smuzhiyun SOC_SINGLE_TLV("Capture PGA Volume", WM8974_INPPGA, 0, 63, 0, inpga_tlv),
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun SOC_SINGLE("Speaker Playback ZC Switch", WM8974_SPKVOL, 7, 1, 0),
162*4882a593Smuzhiyun SOC_SINGLE("Speaker Playback Switch", WM8974_SPKVOL, 6, 1, 1),
163*4882a593Smuzhiyun SOC_SINGLE_TLV("Speaker Playback Volume", WM8974_SPKVOL, 0, 63, 0, spk_tlv),
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun SOC_ENUM("Aux Mode", wm8974_auxmode),
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun SOC_SINGLE("Capture Boost(+20dB)", WM8974_ADCBOOST, 8, 1, 0),
168*4882a593Smuzhiyun SOC_SINGLE("Mono Playback Switch", WM8974_MONOMIX, 6, 1, 1),
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun /* DAC / ADC oversampling */
171*4882a593Smuzhiyun SOC_SINGLE("DAC 128x Oversampling Switch", WM8974_DAC, 8, 1, 0),
172*4882a593Smuzhiyun SOC_SINGLE("ADC 128x Oversampling Switch", WM8974_ADC, 8, 1, 0),
173*4882a593Smuzhiyun };
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun /* Speaker Output Mixer */
176*4882a593Smuzhiyun static const struct snd_kcontrol_new wm8974_speaker_mixer_controls[] = {
177*4882a593Smuzhiyun SOC_DAPM_SINGLE("Line Bypass Switch", WM8974_SPKMIX, 1, 1, 0),
178*4882a593Smuzhiyun SOC_DAPM_SINGLE("Aux Playback Switch", WM8974_SPKMIX, 5, 1, 0),
179*4882a593Smuzhiyun SOC_DAPM_SINGLE("PCM Playback Switch", WM8974_SPKMIX, 0, 1, 0),
180*4882a593Smuzhiyun };
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun /* Mono Output Mixer */
183*4882a593Smuzhiyun static const struct snd_kcontrol_new wm8974_mono_mixer_controls[] = {
184*4882a593Smuzhiyun SOC_DAPM_SINGLE("Line Bypass Switch", WM8974_MONOMIX, 1, 1, 0),
185*4882a593Smuzhiyun SOC_DAPM_SINGLE("Aux Playback Switch", WM8974_MONOMIX, 2, 1, 0),
186*4882a593Smuzhiyun SOC_DAPM_SINGLE("PCM Playback Switch", WM8974_MONOMIX, 0, 1, 0),
187*4882a593Smuzhiyun };
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun /* Boost mixer */
190*4882a593Smuzhiyun static const struct snd_kcontrol_new wm8974_boost_mixer[] = {
191*4882a593Smuzhiyun SOC_DAPM_SINGLE("Aux Switch", WM8974_INPPGA, 6, 1, 1),
192*4882a593Smuzhiyun };
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun /* Input PGA */
195*4882a593Smuzhiyun static const struct snd_kcontrol_new wm8974_inpga[] = {
196*4882a593Smuzhiyun SOC_DAPM_SINGLE("Aux Switch", WM8974_INPUT, 2, 1, 0),
197*4882a593Smuzhiyun SOC_DAPM_SINGLE("MicN Switch", WM8974_INPUT, 1, 1, 0),
198*4882a593Smuzhiyun SOC_DAPM_SINGLE("MicP Switch", WM8974_INPUT, 0, 1, 0),
199*4882a593Smuzhiyun };
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun static const struct snd_soc_dapm_widget wm8974_dapm_widgets[] = {
202*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Speaker Mixer", WM8974_POWER3, 2, 0,
203*4882a593Smuzhiyun &wm8974_speaker_mixer_controls[0],
204*4882a593Smuzhiyun ARRAY_SIZE(wm8974_speaker_mixer_controls)),
205*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Mono Mixer", WM8974_POWER3, 3, 0,
206*4882a593Smuzhiyun &wm8974_mono_mixer_controls[0],
207*4882a593Smuzhiyun ARRAY_SIZE(wm8974_mono_mixer_controls)),
208*4882a593Smuzhiyun SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM8974_POWER3, 0, 0),
209*4882a593Smuzhiyun SND_SOC_DAPM_ADC("ADC", "HiFi Capture", WM8974_POWER2, 0, 0),
210*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Aux Input", WM8974_POWER1, 6, 0, NULL, 0),
211*4882a593Smuzhiyun SND_SOC_DAPM_PGA("SpkN Out", WM8974_POWER3, 5, 0, NULL, 0),
212*4882a593Smuzhiyun SND_SOC_DAPM_PGA("SpkP Out", WM8974_POWER3, 6, 0, NULL, 0),
213*4882a593Smuzhiyun SND_SOC_DAPM_PGA("Mono Out", WM8974_POWER3, 7, 0, NULL, 0),
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Input PGA", WM8974_POWER2, 2, 0, wm8974_inpga,
216*4882a593Smuzhiyun ARRAY_SIZE(wm8974_inpga)),
217*4882a593Smuzhiyun SND_SOC_DAPM_MIXER("Boost Mixer", WM8974_POWER2, 4, 0,
218*4882a593Smuzhiyun wm8974_boost_mixer, ARRAY_SIZE(wm8974_boost_mixer)),
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun SND_SOC_DAPM_SUPPLY("Mic Bias", WM8974_POWER1, 4, 0, NULL, 0),
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("MICN"),
223*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("MICP"),
224*4882a593Smuzhiyun SND_SOC_DAPM_INPUT("AUX"),
225*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("MONOOUT"),
226*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPKOUTP"),
227*4882a593Smuzhiyun SND_SOC_DAPM_OUTPUT("SPKOUTN"),
228*4882a593Smuzhiyun };
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun static const struct snd_soc_dapm_route wm8974_dapm_routes[] = {
231*4882a593Smuzhiyun /* Mono output mixer */
232*4882a593Smuzhiyun {"Mono Mixer", "PCM Playback Switch", "DAC"},
233*4882a593Smuzhiyun {"Mono Mixer", "Aux Playback Switch", "Aux Input"},
234*4882a593Smuzhiyun {"Mono Mixer", "Line Bypass Switch", "Boost Mixer"},
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun /* Speaker output mixer */
237*4882a593Smuzhiyun {"Speaker Mixer", "PCM Playback Switch", "DAC"},
238*4882a593Smuzhiyun {"Speaker Mixer", "Aux Playback Switch", "Aux Input"},
239*4882a593Smuzhiyun {"Speaker Mixer", "Line Bypass Switch", "Boost Mixer"},
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun /* Outputs */
242*4882a593Smuzhiyun {"Mono Out", NULL, "Mono Mixer"},
243*4882a593Smuzhiyun {"MONOOUT", NULL, "Mono Out"},
244*4882a593Smuzhiyun {"SpkN Out", NULL, "Speaker Mixer"},
245*4882a593Smuzhiyun {"SpkP Out", NULL, "Speaker Mixer"},
246*4882a593Smuzhiyun {"SPKOUTN", NULL, "SpkN Out"},
247*4882a593Smuzhiyun {"SPKOUTP", NULL, "SpkP Out"},
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun /* Boost Mixer */
250*4882a593Smuzhiyun {"ADC", NULL, "Boost Mixer"},
251*4882a593Smuzhiyun {"Boost Mixer", "Aux Switch", "Aux Input"},
252*4882a593Smuzhiyun {"Boost Mixer", NULL, "Input PGA"},
253*4882a593Smuzhiyun {"Boost Mixer", NULL, "MICP"},
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun /* Input PGA */
256*4882a593Smuzhiyun {"Input PGA", "Aux Switch", "Aux Input"},
257*4882a593Smuzhiyun {"Input PGA", "MicN Switch", "MICN"},
258*4882a593Smuzhiyun {"Input PGA", "MicP Switch", "MICP"},
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun /* Inputs */
261*4882a593Smuzhiyun {"Aux Input", NULL, "AUX"},
262*4882a593Smuzhiyun };
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun struct pll_ {
265*4882a593Smuzhiyun unsigned int pre_div:1;
266*4882a593Smuzhiyun unsigned int n:4;
267*4882a593Smuzhiyun unsigned int k;
268*4882a593Smuzhiyun };
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun /* The size in bits of the pll divide multiplied by 10
271*4882a593Smuzhiyun * to allow rounding later */
272*4882a593Smuzhiyun #define FIXED_PLL_SIZE ((1 << 24) * 10)
273*4882a593Smuzhiyun
pll_factors(struct pll_ * pll_div,unsigned int target,unsigned int source)274*4882a593Smuzhiyun static void pll_factors(struct pll_ *pll_div,
275*4882a593Smuzhiyun unsigned int target, unsigned int source)
276*4882a593Smuzhiyun {
277*4882a593Smuzhiyun unsigned long long Kpart;
278*4882a593Smuzhiyun unsigned int K, Ndiv, Nmod;
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun /* There is a fixed divide by 4 in the output path */
281*4882a593Smuzhiyun target *= 4;
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun Ndiv = target / source;
284*4882a593Smuzhiyun if (Ndiv < 6) {
285*4882a593Smuzhiyun source /= 2;
286*4882a593Smuzhiyun pll_div->pre_div = 1;
287*4882a593Smuzhiyun Ndiv = target / source;
288*4882a593Smuzhiyun } else
289*4882a593Smuzhiyun pll_div->pre_div = 0;
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun if ((Ndiv < 6) || (Ndiv > 12))
292*4882a593Smuzhiyun printk(KERN_WARNING
293*4882a593Smuzhiyun "WM8974 N value %u outwith recommended range!\n",
294*4882a593Smuzhiyun Ndiv);
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun pll_div->n = Ndiv;
297*4882a593Smuzhiyun Nmod = target % source;
298*4882a593Smuzhiyun Kpart = FIXED_PLL_SIZE * (long long)Nmod;
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun do_div(Kpart, source);
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun K = Kpart & 0xFFFFFFFF;
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun /* Check if we need to round */
305*4882a593Smuzhiyun if ((K % 10) >= 5)
306*4882a593Smuzhiyun K += 5;
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun /* Move down to proper range now rounding is done */
309*4882a593Smuzhiyun K /= 10;
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun pll_div->k = K;
312*4882a593Smuzhiyun }
313*4882a593Smuzhiyun
wm8974_set_dai_pll(struct snd_soc_dai * codec_dai,int pll_id,int source,unsigned int freq_in,unsigned int freq_out)314*4882a593Smuzhiyun static int wm8974_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
315*4882a593Smuzhiyun int source, unsigned int freq_in, unsigned int freq_out)
316*4882a593Smuzhiyun {
317*4882a593Smuzhiyun struct snd_soc_component *component = codec_dai->component;
318*4882a593Smuzhiyun struct pll_ pll_div;
319*4882a593Smuzhiyun u16 reg;
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun if (freq_in == 0 || freq_out == 0) {
322*4882a593Smuzhiyun /* Clock CODEC directly from MCLK */
323*4882a593Smuzhiyun reg = snd_soc_component_read(component, WM8974_CLOCK);
324*4882a593Smuzhiyun snd_soc_component_write(component, WM8974_CLOCK, reg & 0x0ff);
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun /* Turn off PLL */
327*4882a593Smuzhiyun reg = snd_soc_component_read(component, WM8974_POWER1);
328*4882a593Smuzhiyun snd_soc_component_write(component, WM8974_POWER1, reg & 0x1df);
329*4882a593Smuzhiyun return 0;
330*4882a593Smuzhiyun }
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun pll_factors(&pll_div, freq_out, freq_in);
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun snd_soc_component_write(component, WM8974_PLLN, (pll_div.pre_div << 4) | pll_div.n);
335*4882a593Smuzhiyun snd_soc_component_write(component, WM8974_PLLK1, pll_div.k >> 18);
336*4882a593Smuzhiyun snd_soc_component_write(component, WM8974_PLLK2, (pll_div.k >> 9) & 0x1ff);
337*4882a593Smuzhiyun snd_soc_component_write(component, WM8974_PLLK3, pll_div.k & 0x1ff);
338*4882a593Smuzhiyun reg = snd_soc_component_read(component, WM8974_POWER1);
339*4882a593Smuzhiyun snd_soc_component_write(component, WM8974_POWER1, reg | 0x020);
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun /* Run CODEC from PLL instead of MCLK */
342*4882a593Smuzhiyun reg = snd_soc_component_read(component, WM8974_CLOCK);
343*4882a593Smuzhiyun snd_soc_component_write(component, WM8974_CLOCK, reg | 0x100);
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun return 0;
346*4882a593Smuzhiyun }
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun /*
349*4882a593Smuzhiyun * Configure WM8974 clock dividers.
350*4882a593Smuzhiyun */
wm8974_set_dai_clkdiv(struct snd_soc_dai * codec_dai,int div_id,int div)351*4882a593Smuzhiyun static int wm8974_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
352*4882a593Smuzhiyun int div_id, int div)
353*4882a593Smuzhiyun {
354*4882a593Smuzhiyun struct snd_soc_component *component = codec_dai->component;
355*4882a593Smuzhiyun u16 reg;
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun switch (div_id) {
358*4882a593Smuzhiyun case WM8974_OPCLKDIV:
359*4882a593Smuzhiyun reg = snd_soc_component_read(component, WM8974_GPIO) & 0x1cf;
360*4882a593Smuzhiyun snd_soc_component_write(component, WM8974_GPIO, reg | div);
361*4882a593Smuzhiyun break;
362*4882a593Smuzhiyun case WM8974_MCLKDIV:
363*4882a593Smuzhiyun reg = snd_soc_component_read(component, WM8974_CLOCK) & 0x11f;
364*4882a593Smuzhiyun snd_soc_component_write(component, WM8974_CLOCK, reg | div);
365*4882a593Smuzhiyun break;
366*4882a593Smuzhiyun case WM8974_BCLKDIV:
367*4882a593Smuzhiyun reg = snd_soc_component_read(component, WM8974_CLOCK) & 0x1e3;
368*4882a593Smuzhiyun snd_soc_component_write(component, WM8974_CLOCK, reg | div);
369*4882a593Smuzhiyun break;
370*4882a593Smuzhiyun default:
371*4882a593Smuzhiyun return -EINVAL;
372*4882a593Smuzhiyun }
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun return 0;
375*4882a593Smuzhiyun }
376*4882a593Smuzhiyun
wm8974_get_mclkdiv(unsigned int f_in,unsigned int f_out,int * mclkdiv)377*4882a593Smuzhiyun static unsigned int wm8974_get_mclkdiv(unsigned int f_in, unsigned int f_out,
378*4882a593Smuzhiyun int *mclkdiv)
379*4882a593Smuzhiyun {
380*4882a593Smuzhiyun unsigned int ratio = 2 * f_in / f_out;
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun if (ratio <= 2) {
383*4882a593Smuzhiyun *mclkdiv = WM8974_MCLKDIV_1;
384*4882a593Smuzhiyun ratio = 2;
385*4882a593Smuzhiyun } else if (ratio == 3) {
386*4882a593Smuzhiyun *mclkdiv = WM8974_MCLKDIV_1_5;
387*4882a593Smuzhiyun } else if (ratio == 4) {
388*4882a593Smuzhiyun *mclkdiv = WM8974_MCLKDIV_2;
389*4882a593Smuzhiyun } else if (ratio <= 6) {
390*4882a593Smuzhiyun *mclkdiv = WM8974_MCLKDIV_3;
391*4882a593Smuzhiyun ratio = 6;
392*4882a593Smuzhiyun } else if (ratio <= 8) {
393*4882a593Smuzhiyun *mclkdiv = WM8974_MCLKDIV_4;
394*4882a593Smuzhiyun ratio = 8;
395*4882a593Smuzhiyun } else if (ratio <= 12) {
396*4882a593Smuzhiyun *mclkdiv = WM8974_MCLKDIV_6;
397*4882a593Smuzhiyun ratio = 12;
398*4882a593Smuzhiyun } else if (ratio <= 16) {
399*4882a593Smuzhiyun *mclkdiv = WM8974_MCLKDIV_8;
400*4882a593Smuzhiyun ratio = 16;
401*4882a593Smuzhiyun } else {
402*4882a593Smuzhiyun *mclkdiv = WM8974_MCLKDIV_12;
403*4882a593Smuzhiyun ratio = 24;
404*4882a593Smuzhiyun }
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun return f_out * ratio / 2;
407*4882a593Smuzhiyun }
408*4882a593Smuzhiyun
wm8974_update_clocks(struct snd_soc_dai * dai)409*4882a593Smuzhiyun static int wm8974_update_clocks(struct snd_soc_dai *dai)
410*4882a593Smuzhiyun {
411*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
412*4882a593Smuzhiyun struct wm8974_priv *priv = snd_soc_component_get_drvdata(component);
413*4882a593Smuzhiyun unsigned int fs256;
414*4882a593Smuzhiyun unsigned int fpll = 0;
415*4882a593Smuzhiyun unsigned int f;
416*4882a593Smuzhiyun int mclkdiv;
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun if (!priv->mclk || !priv->fs)
419*4882a593Smuzhiyun return 0;
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun fs256 = 256 * priv->fs;
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun f = wm8974_get_mclkdiv(priv->mclk, fs256, &mclkdiv);
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun if (f != priv->mclk) {
426*4882a593Smuzhiyun /* The PLL performs best around 90MHz */
427*4882a593Smuzhiyun fpll = wm8974_get_mclkdiv(22500000, fs256, &mclkdiv);
428*4882a593Smuzhiyun }
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun wm8974_set_dai_pll(dai, 0, 0, priv->mclk, fpll);
431*4882a593Smuzhiyun wm8974_set_dai_clkdiv(dai, WM8974_MCLKDIV, mclkdiv);
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun return 0;
434*4882a593Smuzhiyun }
435*4882a593Smuzhiyun
wm8974_set_dai_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)436*4882a593Smuzhiyun static int wm8974_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
437*4882a593Smuzhiyun unsigned int freq, int dir)
438*4882a593Smuzhiyun {
439*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
440*4882a593Smuzhiyun struct wm8974_priv *priv = snd_soc_component_get_drvdata(component);
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun if (dir != SND_SOC_CLOCK_IN)
443*4882a593Smuzhiyun return -EINVAL;
444*4882a593Smuzhiyun
445*4882a593Smuzhiyun priv->mclk = freq;
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun return wm8974_update_clocks(dai);
448*4882a593Smuzhiyun }
449*4882a593Smuzhiyun
wm8974_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)450*4882a593Smuzhiyun static int wm8974_set_dai_fmt(struct snd_soc_dai *codec_dai,
451*4882a593Smuzhiyun unsigned int fmt)
452*4882a593Smuzhiyun {
453*4882a593Smuzhiyun struct snd_soc_component *component = codec_dai->component;
454*4882a593Smuzhiyun u16 iface = 0;
455*4882a593Smuzhiyun u16 clk = snd_soc_component_read(component, WM8974_CLOCK) & 0x1fe;
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun /* set master/slave audio interface */
458*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
459*4882a593Smuzhiyun case SND_SOC_DAIFMT_CBM_CFM:
460*4882a593Smuzhiyun clk |= 0x0001;
461*4882a593Smuzhiyun break;
462*4882a593Smuzhiyun case SND_SOC_DAIFMT_CBS_CFS:
463*4882a593Smuzhiyun break;
464*4882a593Smuzhiyun default:
465*4882a593Smuzhiyun return -EINVAL;
466*4882a593Smuzhiyun }
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun /* interface format */
469*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
470*4882a593Smuzhiyun case SND_SOC_DAIFMT_I2S:
471*4882a593Smuzhiyun iface |= 0x0010;
472*4882a593Smuzhiyun break;
473*4882a593Smuzhiyun case SND_SOC_DAIFMT_RIGHT_J:
474*4882a593Smuzhiyun break;
475*4882a593Smuzhiyun case SND_SOC_DAIFMT_LEFT_J:
476*4882a593Smuzhiyun iface |= 0x0008;
477*4882a593Smuzhiyun break;
478*4882a593Smuzhiyun case SND_SOC_DAIFMT_DSP_A:
479*4882a593Smuzhiyun if ((fmt & SND_SOC_DAIFMT_INV_MASK) == SND_SOC_DAIFMT_IB_IF ||
480*4882a593Smuzhiyun (fmt & SND_SOC_DAIFMT_INV_MASK) == SND_SOC_DAIFMT_NB_IF) {
481*4882a593Smuzhiyun return -EINVAL;
482*4882a593Smuzhiyun }
483*4882a593Smuzhiyun iface |= 0x00018;
484*4882a593Smuzhiyun break;
485*4882a593Smuzhiyun default:
486*4882a593Smuzhiyun return -EINVAL;
487*4882a593Smuzhiyun }
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun /* clock inversion */
490*4882a593Smuzhiyun switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
491*4882a593Smuzhiyun case SND_SOC_DAIFMT_NB_NF:
492*4882a593Smuzhiyun break;
493*4882a593Smuzhiyun case SND_SOC_DAIFMT_IB_IF:
494*4882a593Smuzhiyun iface |= 0x0180;
495*4882a593Smuzhiyun break;
496*4882a593Smuzhiyun case SND_SOC_DAIFMT_IB_NF:
497*4882a593Smuzhiyun iface |= 0x0100;
498*4882a593Smuzhiyun break;
499*4882a593Smuzhiyun case SND_SOC_DAIFMT_NB_IF:
500*4882a593Smuzhiyun iface |= 0x0080;
501*4882a593Smuzhiyun break;
502*4882a593Smuzhiyun default:
503*4882a593Smuzhiyun return -EINVAL;
504*4882a593Smuzhiyun }
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun snd_soc_component_write(component, WM8974_IFACE, iface);
507*4882a593Smuzhiyun snd_soc_component_write(component, WM8974_CLOCK, clk);
508*4882a593Smuzhiyun return 0;
509*4882a593Smuzhiyun }
510*4882a593Smuzhiyun
wm8974_pcm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)511*4882a593Smuzhiyun static int wm8974_pcm_hw_params(struct snd_pcm_substream *substream,
512*4882a593Smuzhiyun struct snd_pcm_hw_params *params,
513*4882a593Smuzhiyun struct snd_soc_dai *dai)
514*4882a593Smuzhiyun {
515*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
516*4882a593Smuzhiyun struct wm8974_priv *priv = snd_soc_component_get_drvdata(component);
517*4882a593Smuzhiyun u16 iface = snd_soc_component_read(component, WM8974_IFACE) & 0x19f;
518*4882a593Smuzhiyun u16 adn = snd_soc_component_read(component, WM8974_ADD) & 0x1f1;
519*4882a593Smuzhiyun int err;
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun priv->fs = params_rate(params);
522*4882a593Smuzhiyun err = wm8974_update_clocks(dai);
523*4882a593Smuzhiyun if (err)
524*4882a593Smuzhiyun return err;
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun /* bit size */
527*4882a593Smuzhiyun switch (params_width(params)) {
528*4882a593Smuzhiyun case 16:
529*4882a593Smuzhiyun break;
530*4882a593Smuzhiyun case 20:
531*4882a593Smuzhiyun iface |= 0x0020;
532*4882a593Smuzhiyun break;
533*4882a593Smuzhiyun case 24:
534*4882a593Smuzhiyun iface |= 0x0040;
535*4882a593Smuzhiyun break;
536*4882a593Smuzhiyun case 32:
537*4882a593Smuzhiyun iface |= 0x0060;
538*4882a593Smuzhiyun break;
539*4882a593Smuzhiyun }
540*4882a593Smuzhiyun
541*4882a593Smuzhiyun /* filter coefficient */
542*4882a593Smuzhiyun switch (params_rate(params)) {
543*4882a593Smuzhiyun case 8000:
544*4882a593Smuzhiyun adn |= 0x5 << 1;
545*4882a593Smuzhiyun break;
546*4882a593Smuzhiyun case 11025:
547*4882a593Smuzhiyun adn |= 0x4 << 1;
548*4882a593Smuzhiyun break;
549*4882a593Smuzhiyun case 16000:
550*4882a593Smuzhiyun adn |= 0x3 << 1;
551*4882a593Smuzhiyun break;
552*4882a593Smuzhiyun case 22050:
553*4882a593Smuzhiyun adn |= 0x2 << 1;
554*4882a593Smuzhiyun break;
555*4882a593Smuzhiyun case 32000:
556*4882a593Smuzhiyun adn |= 0x1 << 1;
557*4882a593Smuzhiyun break;
558*4882a593Smuzhiyun case 44100:
559*4882a593Smuzhiyun case 48000:
560*4882a593Smuzhiyun break;
561*4882a593Smuzhiyun }
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun snd_soc_component_write(component, WM8974_IFACE, iface);
564*4882a593Smuzhiyun snd_soc_component_write(component, WM8974_ADD, adn);
565*4882a593Smuzhiyun return 0;
566*4882a593Smuzhiyun }
567*4882a593Smuzhiyun
wm8974_mute(struct snd_soc_dai * dai,int mute,int direction)568*4882a593Smuzhiyun static int wm8974_mute(struct snd_soc_dai *dai, int mute, int direction)
569*4882a593Smuzhiyun {
570*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
571*4882a593Smuzhiyun u16 mute_reg = snd_soc_component_read(component, WM8974_DAC) & 0xffbf;
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun if (mute)
574*4882a593Smuzhiyun snd_soc_component_write(component, WM8974_DAC, mute_reg | 0x40);
575*4882a593Smuzhiyun else
576*4882a593Smuzhiyun snd_soc_component_write(component, WM8974_DAC, mute_reg);
577*4882a593Smuzhiyun return 0;
578*4882a593Smuzhiyun }
579*4882a593Smuzhiyun
580*4882a593Smuzhiyun /* liam need to make this lower power with dapm */
wm8974_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)581*4882a593Smuzhiyun static int wm8974_set_bias_level(struct snd_soc_component *component,
582*4882a593Smuzhiyun enum snd_soc_bias_level level)
583*4882a593Smuzhiyun {
584*4882a593Smuzhiyun u16 power1 = snd_soc_component_read(component, WM8974_POWER1) & ~0x3;
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun switch (level) {
587*4882a593Smuzhiyun case SND_SOC_BIAS_ON:
588*4882a593Smuzhiyun case SND_SOC_BIAS_PREPARE:
589*4882a593Smuzhiyun power1 |= 0x1; /* VMID 50k */
590*4882a593Smuzhiyun snd_soc_component_write(component, WM8974_POWER1, power1);
591*4882a593Smuzhiyun break;
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun case SND_SOC_BIAS_STANDBY:
594*4882a593Smuzhiyun power1 |= WM8974_POWER1_BIASEN | WM8974_POWER1_BUFIOEN;
595*4882a593Smuzhiyun
596*4882a593Smuzhiyun if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
597*4882a593Smuzhiyun regcache_sync(dev_get_regmap(component->dev, NULL));
598*4882a593Smuzhiyun
599*4882a593Smuzhiyun /* Initial cap charge at VMID 5k */
600*4882a593Smuzhiyun snd_soc_component_write(component, WM8974_POWER1, power1 | 0x3);
601*4882a593Smuzhiyun mdelay(100);
602*4882a593Smuzhiyun }
603*4882a593Smuzhiyun
604*4882a593Smuzhiyun power1 |= 0x2; /* VMID 500k */
605*4882a593Smuzhiyun snd_soc_component_write(component, WM8974_POWER1, power1);
606*4882a593Smuzhiyun break;
607*4882a593Smuzhiyun
608*4882a593Smuzhiyun case SND_SOC_BIAS_OFF:
609*4882a593Smuzhiyun snd_soc_component_write(component, WM8974_POWER1, 0);
610*4882a593Smuzhiyun snd_soc_component_write(component, WM8974_POWER2, 0);
611*4882a593Smuzhiyun snd_soc_component_write(component, WM8974_POWER3, 0);
612*4882a593Smuzhiyun break;
613*4882a593Smuzhiyun }
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun return 0;
616*4882a593Smuzhiyun }
617*4882a593Smuzhiyun
wm8974_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)618*4882a593Smuzhiyun static int wm8974_startup(struct snd_pcm_substream *substream,
619*4882a593Smuzhiyun struct snd_soc_dai *dai)
620*4882a593Smuzhiyun {
621*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
622*4882a593Smuzhiyun struct wm8974_priv *priv = snd_soc_component_get_drvdata(component);
623*4882a593Smuzhiyun u16 power1 = snd_soc_component_read(component, WM8974_POWER1);
624*4882a593Smuzhiyun
625*4882a593Smuzhiyun clk_prepare_enable(priv->mclk_in);
626*4882a593Smuzhiyun if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
627*4882a593Smuzhiyun power1 |= 0x10;
628*4882a593Smuzhiyun snd_soc_component_write(component, WM8974_POWER1, power1);
629*4882a593Smuzhiyun }
630*4882a593Smuzhiyun
631*4882a593Smuzhiyun return 0;
632*4882a593Smuzhiyun }
633*4882a593Smuzhiyun
wm8974_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)634*4882a593Smuzhiyun static void wm8974_shutdown(struct snd_pcm_substream *substream,
635*4882a593Smuzhiyun struct snd_soc_dai *dai)
636*4882a593Smuzhiyun {
637*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
638*4882a593Smuzhiyun struct wm8974_priv *priv = snd_soc_component_get_drvdata(component);
639*4882a593Smuzhiyun u16 power1 = snd_soc_component_read(component, WM8974_POWER1);
640*4882a593Smuzhiyun
641*4882a593Smuzhiyun if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
642*4882a593Smuzhiyun power1 &= ~0x10;
643*4882a593Smuzhiyun snd_soc_component_write(component, WM8974_POWER1, power1);
644*4882a593Smuzhiyun }
645*4882a593Smuzhiyun clk_disable_unprepare(priv->mclk_in);
646*4882a593Smuzhiyun }
647*4882a593Smuzhiyun
648*4882a593Smuzhiyun #define WM8974_RATES (SNDRV_PCM_RATE_8000_48000)
649*4882a593Smuzhiyun
650*4882a593Smuzhiyun #define WM8974_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
651*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S24_LE)
652*4882a593Smuzhiyun
653*4882a593Smuzhiyun static const struct snd_soc_dai_ops wm8974_ops = {
654*4882a593Smuzhiyun .hw_params = wm8974_pcm_hw_params,
655*4882a593Smuzhiyun .mute_stream = wm8974_mute,
656*4882a593Smuzhiyun .set_fmt = wm8974_set_dai_fmt,
657*4882a593Smuzhiyun .set_clkdiv = wm8974_set_dai_clkdiv,
658*4882a593Smuzhiyun .set_pll = wm8974_set_dai_pll,
659*4882a593Smuzhiyun .set_sysclk = wm8974_set_dai_sysclk,
660*4882a593Smuzhiyun .startup = wm8974_startup,
661*4882a593Smuzhiyun .shutdown = wm8974_shutdown,
662*4882a593Smuzhiyun .no_capture_mute = 1,
663*4882a593Smuzhiyun };
664*4882a593Smuzhiyun
665*4882a593Smuzhiyun static struct snd_soc_dai_driver wm8974_dai = {
666*4882a593Smuzhiyun .name = "wm8974-hifi",
667*4882a593Smuzhiyun .playback = {
668*4882a593Smuzhiyun .stream_name = "Playback",
669*4882a593Smuzhiyun .channels_min = 1,
670*4882a593Smuzhiyun .channels_max = 2, /* Only 1 channel of data */
671*4882a593Smuzhiyun .rates = WM8974_RATES,
672*4882a593Smuzhiyun .formats = WM8974_FORMATS,},
673*4882a593Smuzhiyun .capture = {
674*4882a593Smuzhiyun .stream_name = "Capture",
675*4882a593Smuzhiyun .channels_min = 1,
676*4882a593Smuzhiyun .channels_max = 2, /* Only 1 channel of data */
677*4882a593Smuzhiyun .rates = WM8974_RATES,
678*4882a593Smuzhiyun .formats = WM8974_FORMATS,},
679*4882a593Smuzhiyun .ops = &wm8974_ops,
680*4882a593Smuzhiyun .symmetric_rates = 1,
681*4882a593Smuzhiyun };
682*4882a593Smuzhiyun
683*4882a593Smuzhiyun static const struct regmap_config wm8974_regmap = {
684*4882a593Smuzhiyun .reg_bits = 7,
685*4882a593Smuzhiyun .val_bits = 9,
686*4882a593Smuzhiyun
687*4882a593Smuzhiyun .max_register = WM8974_MONOMIX,
688*4882a593Smuzhiyun .reg_defaults = wm8974_reg_defaults,
689*4882a593Smuzhiyun .num_reg_defaults = ARRAY_SIZE(wm8974_reg_defaults),
690*4882a593Smuzhiyun .cache_type = REGCACHE_FLAT,
691*4882a593Smuzhiyun };
692*4882a593Smuzhiyun
wm8974_probe(struct snd_soc_component * component)693*4882a593Smuzhiyun static int wm8974_probe(struct snd_soc_component *component)
694*4882a593Smuzhiyun {
695*4882a593Smuzhiyun int ret = 0;
696*4882a593Smuzhiyun
697*4882a593Smuzhiyun ret = wm8974_reset(component);
698*4882a593Smuzhiyun if (ret < 0) {
699*4882a593Smuzhiyun dev_err(component->dev, "Failed to issue reset\n");
700*4882a593Smuzhiyun return ret;
701*4882a593Smuzhiyun }
702*4882a593Smuzhiyun
703*4882a593Smuzhiyun return 0;
704*4882a593Smuzhiyun }
705*4882a593Smuzhiyun
706*4882a593Smuzhiyun static const struct snd_soc_component_driver soc_component_dev_wm8974 = {
707*4882a593Smuzhiyun .probe = wm8974_probe,
708*4882a593Smuzhiyun .set_bias_level = wm8974_set_bias_level,
709*4882a593Smuzhiyun .controls = wm8974_snd_controls,
710*4882a593Smuzhiyun .num_controls = ARRAY_SIZE(wm8974_snd_controls),
711*4882a593Smuzhiyun .dapm_widgets = wm8974_dapm_widgets,
712*4882a593Smuzhiyun .num_dapm_widgets = ARRAY_SIZE(wm8974_dapm_widgets),
713*4882a593Smuzhiyun .dapm_routes = wm8974_dapm_routes,
714*4882a593Smuzhiyun .num_dapm_routes = ARRAY_SIZE(wm8974_dapm_routes),
715*4882a593Smuzhiyun .suspend_bias_off = 1,
716*4882a593Smuzhiyun .idle_bias_on = 1,
717*4882a593Smuzhiyun .use_pmdown_time = 1,
718*4882a593Smuzhiyun .endianness = 1,
719*4882a593Smuzhiyun .non_legacy_dai_naming = 1,
720*4882a593Smuzhiyun };
721*4882a593Smuzhiyun
wm8974_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)722*4882a593Smuzhiyun static int wm8974_i2c_probe(struct i2c_client *i2c,
723*4882a593Smuzhiyun const struct i2c_device_id *id)
724*4882a593Smuzhiyun {
725*4882a593Smuzhiyun struct wm8974_priv *priv;
726*4882a593Smuzhiyun struct regmap *regmap;
727*4882a593Smuzhiyun int ret;
728*4882a593Smuzhiyun
729*4882a593Smuzhiyun priv = devm_kzalloc(&i2c->dev, sizeof(*priv), GFP_KERNEL);
730*4882a593Smuzhiyun if (!priv)
731*4882a593Smuzhiyun return -ENOMEM;
732*4882a593Smuzhiyun
733*4882a593Smuzhiyun i2c_set_clientdata(i2c, priv);
734*4882a593Smuzhiyun
735*4882a593Smuzhiyun regmap = devm_regmap_init_i2c(i2c, &wm8974_regmap);
736*4882a593Smuzhiyun if (IS_ERR(regmap))
737*4882a593Smuzhiyun return PTR_ERR(regmap);
738*4882a593Smuzhiyun
739*4882a593Smuzhiyun priv->mclk_in = devm_clk_get(&i2c->dev, "mclk");
740*4882a593Smuzhiyun if (IS_ERR(priv->mclk_in))
741*4882a593Smuzhiyun return PTR_ERR(priv->mclk_in);
742*4882a593Smuzhiyun
743*4882a593Smuzhiyun ret = devm_snd_soc_register_component(&i2c->dev,
744*4882a593Smuzhiyun &soc_component_dev_wm8974, &wm8974_dai, 1);
745*4882a593Smuzhiyun
746*4882a593Smuzhiyun return ret;
747*4882a593Smuzhiyun }
748*4882a593Smuzhiyun
749*4882a593Smuzhiyun static const struct i2c_device_id wm8974_i2c_id[] = {
750*4882a593Smuzhiyun { "wm8974", 0 },
751*4882a593Smuzhiyun { }
752*4882a593Smuzhiyun };
753*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, wm8974_i2c_id);
754*4882a593Smuzhiyun
755*4882a593Smuzhiyun static const struct of_device_id wm8974_of_match[] = {
756*4882a593Smuzhiyun { .compatible = "wlf,wm8974", },
757*4882a593Smuzhiyun { }
758*4882a593Smuzhiyun };
759*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, wm8974_of_match);
760*4882a593Smuzhiyun
761*4882a593Smuzhiyun static struct i2c_driver wm8974_i2c_driver = {
762*4882a593Smuzhiyun .driver = {
763*4882a593Smuzhiyun .name = "wm8974",
764*4882a593Smuzhiyun .of_match_table = wm8974_of_match,
765*4882a593Smuzhiyun },
766*4882a593Smuzhiyun .probe = wm8974_i2c_probe,
767*4882a593Smuzhiyun .id_table = wm8974_i2c_id,
768*4882a593Smuzhiyun };
769*4882a593Smuzhiyun
770*4882a593Smuzhiyun module_i2c_driver(wm8974_i2c_driver);
771*4882a593Smuzhiyun
772*4882a593Smuzhiyun MODULE_DESCRIPTION("ASoC WM8974 driver");
773*4882a593Smuzhiyun MODULE_AUTHOR("Liam Girdwood");
774*4882a593Smuzhiyun MODULE_LICENSE("GPL");
775