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Searched refs:phy_write (Results 1 – 25 of 147) sorted by relevance

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/OK3568_Linux_fs/kernel/drivers/net/phy/
H A Drk630phy.c120 phy_write(phydev, REG_PAGE_SEL, 0x0000); in rk630_phy_wol_enable()
121 phy_write(phydev, REG_MAC_ADDRESS0, ((u16)ndev->dev_addr[0] << 8) + ndev->dev_addr[1]); in rk630_phy_wol_enable()
122 phy_write(phydev, REG_MAC_ADDRESS1, ((u16)ndev->dev_addr[2] << 8) + ndev->dev_addr[3]); in rk630_phy_wol_enable()
123 phy_write(phydev, REG_MAC_ADDRESS2, ((u16)ndev->dev_addr[4] << 8) + ndev->dev_addr[5]); in rk630_phy_wol_enable()
129 phy_write(phydev, REG_GLOBAL_CONFIGURATION, value); in rk630_phy_wol_enable()
133 phy_write(phydev, REG_INTERRUPT_MASK, value); in rk630_phy_wol_enable()
141 phy_write(phydev, REG_PAGE_SEL, 0x0000); in rk630_phy_wol_disable()
144 phy_write(phydev, REG_GLOBAL_CONFIGURATION, value); in rk630_phy_wol_disable()
152 phy_write(phydev, REG_PAGE_SEL, 0x0100); in rk630_phy_ieee_set()
158 phy_write(phydev, REG_PAGE1_EEE_CONFIGURE, value); in rk630_phy_ieee_set()
[all …]
H A Dvitesse.c94 err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon); in vsc824x_add_skew()
103 err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT, in vsc824x_config_init()
129 phy_write(phydev, 0x1f, 0x2a30); in vsc73xx_config_init()
131 phy_write(phydev, 0x1f, 0x0000); in vsc73xx_config_init()
145 phy_write(phydev, 0x1f, 0x2a30); in vsc738x_config_init()
147 phy_write(phydev, 0x1f, 0x52b5); in vsc738x_config_init()
148 phy_write(phydev, 0x10, 0xb68a); in vsc738x_config_init()
151 phy_write(phydev, 0x10, 0x968a); in vsc738x_config_init()
152 phy_write(phydev, 0x1f, 0x2a30); in vsc738x_config_init()
154 phy_write(phydev, 0x1f, 0x0000); in vsc738x_config_init()
[all …]
H A Dnational.c56 phy_write(phydev, NS_EXP_MEM_ADD, reg); in ns_exp_read()
62 phy_write(phydev, NS_EXP_MEM_ADD, reg); in ns_exp_write()
63 phy_write(phydev, NS_EXP_MEM_DATA, data); in ns_exp_write()
71 err = phy_write(phydev, DP83865_INT_MASK, in ns_config_intr()
74 err = phy_write(phydev, DP83865_INT_MASK, 0); in ns_config_intr()
87 ret = phy_write(phydev, DP83865_INT_CLEAR, ret & ~0x7); in ns_ack_interrupt()
96 phy_write(phydev, MII_BMCR, (bmcr | BMCR_PDOWN)); in ns_giga_speed_fallback()
99 phy_write(phydev, NS_EXP_MEM_CTL, 0); in ns_giga_speed_fallback()
100 phy_write(phydev, NS_EXP_MEM_ADD, 0x1C0); in ns_giga_speed_fallback()
101 phy_write(phydev, NS_EXP_MEM_DATA, 0x0008); in ns_giga_speed_fallback()
[all …]
H A Dbcm7xxx.c80 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_d0_afe_config_init()
108 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_e0_plus_afe_config_init()
266 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_BIAS_TRIM, 0x3BE0); in bcm7xxx_28nm_ephy_01_afe_config_init()
271 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_01_afe_config_init()
281 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_01_afe_config_init()
337 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
341 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
347 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
351 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT, in bcm7xxx_28nm_ephy_eee_enable()
356 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL, in bcm7xxx_28nm_ephy_eee_enable()
[all …]
H A Drockchip.c47 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_ENABLE); in rockchip_init_tstmode()
51 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_DISABLE); in rockchip_init_tstmode()
55 return phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_ENABLE); in rockchip_init_tstmode()
61 return phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_DISABLE); in rockchip_close_tstmode()
76 ret = phy_write(phydev, SMI_ADDR_TSTWRITE, 0xB); in rockchip_integrated_phy_analog_init()
79 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTCNTL_WR | WR_ADDR_A7CFG); in rockchip_integrated_phy_analog_init()
98 ret = phy_write(phydev, MII_INTERNAL_CTRL_STATUS, val); in rockchip_integrated_phy_config_init()
147 err = phy_write(phydev, MII_INTERNAL_CTRL_STATUS, val); in rockchip_set_polarity()
H A Dmeson-gxl.c55 ret = phy_write(phydev, TSTCNTL, 0); in meson_gxl_open_banks()
58 ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE); in meson_gxl_open_banks()
61 ret = phy_write(phydev, TSTCNTL, 0); in meson_gxl_open_banks()
64 return phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE); in meson_gxl_open_banks()
69 phy_write(phydev, TSTCNTL, 0); in meson_gxl_close_banks()
81 ret = phy_write(phydev, TSTCNTL, TSTCNTL_READ | in meson_gxl_read_reg()
105 ret = phy_write(phydev, TSTWRITE, value); in meson_gxl_write_reg()
109 ret = phy_write(phydev, TSTCNTL, TSTCNTL_WRITE | in meson_gxl_write_reg()
222 return phy_write(phydev, INTSRC_MASK, val); in meson_gxl_config_intr()
H A Ddp83tc811.c213 err = phy_write(phydev, MII_DP83811_INT_STAT1, misr_status); in dp83811_config_intr()
228 err = phy_write(phydev, MII_DP83811_INT_STAT2, misr_status); in dp83811_config_intr()
240 err = phy_write(phydev, MII_DP83811_INT_STAT3, misr_status); in dp83811_config_intr()
243 err = phy_write(phydev, MII_DP83811_INT_STAT1, 0); in dp83811_config_intr()
247 err = phy_write(phydev, MII_DP83811_INT_STAT2, 0); in dp83811_config_intr()
251 err = phy_write(phydev, MII_DP83811_INT_STAT3, 0); in dp83811_config_intr()
264 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_aneg()
269 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_aneg()
285 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_init()
288 err = phy_write(phydev, MII_DP83811_SGMII_CTRL, in dp83811_config_init()
[all …]
/OK3568_Linux_fs/u-boot/drivers/net/phy/
H A Dmarvell.c111 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in m88e1011s_config()
113 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); in m88e1011s_config()
114 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c); in m88e1011s_config()
115 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); in m88e1011s_config()
116 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0); in m88e1011s_config()
117 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); in m88e1011s_config()
119 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in m88e1011s_config()
216 phy_write(phydev, in m88e1111s_config()
229 phy_write(phydev, in m88e1111s_config()
241 phy_write(phydev, MDIO_DEVAD_NONE, in m88e1111s_config()
[all …]
H A Drk630phy.c139 phy_write(phydev, 0, MDIO_DEVAD_NONE, in rk630_phy_s40_config_init()
143 phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE_SEL, 0x0100); in rk630_phy_s40_config_init()
145 phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE1_APS_CTRL, 0x4824); in rk630_phy_s40_config_init()
147 phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE_SEL, 0x0200); in rk630_phy_s40_config_init()
149 phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE2_AFE_CTRL, 0x0000); in rk630_phy_s40_config_init()
151 phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE_SEL, 0x0600); in rk630_phy_s40_config_init()
153 phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE6_AFE_TX_CTRL, 0x708f); in rk630_phy_s40_config_init()
155 phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE6_AFE_RX_CTRL, 0xf000); in rk630_phy_s40_config_init()
156 phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE6_AFE_DRIVER2, 0x1530); in rk630_phy_s40_config_init()
159 phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE_SEL, 0x0800); in rk630_phy_s40_config_init()
[all …]
H A Datheros.c22 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); in ar8021_config()
23 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47); in ar8021_config()
33 phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, in ar8031_config()
35 phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, in ar8031_config()
41 phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, in ar8031_config()
43 phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, in ar8031_config()
59 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x0007); in ar8035_config()
60 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); in ar8035_config()
61 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); in ar8035_config()
63 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, (regval|0x0018)); in ar8035_config()
[all …]
H A Dvitesse.c73 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT, in vitesse_config()
76 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_EXT_CON1, in vitesse_config()
125 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT, in cis8204_config()
131 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS8204_EPHY_CON, in cis8204_config()
135 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS8204_EPHY_CON, in cis8204_config()
154 return phy_write(phydev, MDIO_DEVAD_NONE, MII_VSC8601_EPHY_CTL, ret); in vsc8601_add_skew()
174 phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, in vsc8574_config()
181 phy_write(phydev, MDIO_DEVAD_NONE, in vsc8574_config()
184 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL18, in vsc8574_config()
189 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8574_GENERAL19, val); in vsc8574_config()
[all …]
H A Dbroadcom.c43 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, in bcm_phy_write_misc()
48 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, reg_val); in bcm_phy_write_misc()
51 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL, reg_val); in bcm_phy_write_misc()
53 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA, value); in bcm_phy_write_misc()
140 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg); in bcm5482_config()
143 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, in bcm5482_config()
147 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, reg); in bcm5482_config()
150 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_SHD, in bcm5482_config()
153 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL, in bcm5482_config()
155 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA, in bcm5482_config()
[all …]
H A Dmscc.c142 phy_write(phydev, MDIO_DEVAD_NONE, in mscc_vsc8531_vsc8541_init_scripts()
147 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
154 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17, reg_val); in mscc_vsc8531_vsc8541_init_scripts()
155 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
160 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
168 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18, reg_val); in mscc_vsc8531_vsc8541_init_scripts()
169 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
174 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
182 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18, reg_val); in mscc_vsc8531_vsc8541_init_scripts()
188 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17, reg_val); in mscc_vsc8531_vsc8541_init_scripts()
[all …]
H A Dti.c122 phy_write(phydev, addr, MII_MMD_CTRL, devad); in phy_read_mmd_indirect()
125 phy_write(phydev, addr, MII_MMD_DATA, prtad); in phy_read_mmd_indirect()
128 phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); in phy_read_mmd_indirect()
155 phy_write(phydev, addr, MII_MMD_CTRL, devad); in phy_write_mmd_indirect()
158 phy_write(phydev, addr, MII_MMD_DATA, prtad); in phy_write_mmd_indirect()
161 phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); in phy_write_mmd_indirect()
164 phy_write(phydev, addr, MII_MMD_DATA, data); in phy_write_mmd_indirect()
233 phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL, in dp83867_config()
237 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL, in dp83867_config()
243 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, in dp83867_config()
[all …]
H A Drealtek.c66 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in rtl8211x_config()
71 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER, in rtl8211x_config()
82 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, reg); in rtl8211x_config()
96 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in rtl8211f_config()
98 phy_write(phydev, MDIO_DEVAD_NONE, in rtl8211f_config()
109 phy_write(phydev, MDIO_DEVAD_NONE, 0x11, reg); in rtl8211f_config()
111 phy_write(phydev, MDIO_DEVAD_NONE, in rtl8211f_config()
115 phy_write(phydev, MDIO_DEVAD_NONE, in rtl8211f_config()
117 phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x617f); in rtl8211f_config()
118 phy_write(phydev, MDIO_DEVAD_NONE, in rtl8211f_config()
[all …]
H A Dmicrel_ksz90x1.c222 phy_write(phydev, MDIO_DEVAD_NONE, in ksz9021_phy_extended_write()
224 return phy_write(phydev, MDIO_DEVAD_NONE, in ksz9021_phy_extended_write()
231 phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_CTRL, regnum); in ksz9021_phy_extended_read()
270 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, ctrl1000); in ksz9021_config()
295 phy_write(phydev, MDIO_DEVAD_NONE, in ksz9031_phy_extended_write()
298 phy_write(phydev, MDIO_DEVAD_NONE, in ksz9031_phy_extended_write()
301 phy_write(phydev, MDIO_DEVAD_NONE, in ksz9031_phy_extended_write()
304 return phy_write(phydev, MDIO_DEVAD_NONE, in ksz9031_phy_extended_write()
311 phy_write(phydev, MDIO_DEVAD_NONE, in ksz9031_phy_extended_read()
313 phy_write(phydev, MDIO_DEVAD_NONE, in ksz9031_phy_extended_read()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/realtek/
H A Dr8169_phy_config.c285 phy_write(phydev, 0x1f, 0x0001); in rtl8168bb_hw_phy_config()
287 phy_write(phydev, 0x10, 0xf41b); in rtl8168bb_hw_phy_config()
288 phy_write(phydev, 0x1f, 0x0000); in rtl8168bb_hw_phy_config()
300 phy_write(phydev, 0x1d, 0x0f00); in rtl8168cp_1_hw_phy_config()
447 phy_write(phydev, 0x1f, 0x0005); in rtl8168d_apply_firmware_cond()
448 phy_write(phydev, 0x05, 0x001b); in rtl8168d_apply_firmware_cond()
450 phy_write(phydev, 0x1f, 0x0000); in rtl8168d_apply_firmware_cond()
467 phy_write(phydev, 0x1f, 0x0002); in rtl8168d_1_hw_phy_config()
485 phy_write(phydev, 0x1f, 0x0002); in rtl8168d_1_hw_phy_config()
489 phy_write(phydev, 0x0d, val | set[i]); in rtl8168d_1_hw_phy_config()
[all …]
/OK3568_Linux_fs/u-boot/drivers/video/drm/
H A Dsamsung_mipi_dcphy.c1201 phy_write(struct samsung_mipi_dcphy *samsung, u32 reg, u32 val) in phy_write() function
1219 phy_write(samsung, reg, tmp); in phy_update_bits()
1272 phy_write(samsung, BIAS_CON0, 0x0010); in samsung_mipi_dcphy_bias_block_enable()
1273 phy_write(samsung, BIAS_CON1, 0x0110); in samsung_mipi_dcphy_bias_block_enable()
1274 phy_write(samsung, BIAS_CON2, 0x3223); in samsung_mipi_dcphy_bias_block_enable()
1296 phy_write(samsung, PLL_CON1, dsm_tmp); in samsung_mipi_dcphy_pll_configure()
1298 phy_write(samsung, PLL_CON1, samsung->pll.dsm); in samsung_mipi_dcphy_pll_configure()
1304 phy_write(samsung, PLL_CON3, in samsung_mipi_dcphy_pll_configure()
1309 phy_write(samsung, PLL_CON5, RESET_N_SEL | PLL_ENABLE_SEL); in samsung_mipi_dcphy_pll_configure()
1310 phy_write(samsung, PLL_CON7, PLL_LOCK_CNT(0xf000)); in samsung_mipi_dcphy_pll_configure()
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-imx/
H A Dmach-imx6q.c28 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, in ksz9021rn_phy_fixup()
30 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000); in ksz9021rn_phy_fixup()
33 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, in ksz9021rn_phy_fixup()
35 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xf0f0); in ksz9021rn_phy_fixup()
36 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, in ksz9021rn_phy_fixup()
45 phy_write(dev, 0x0d, device); in mmd_write_reg()
46 phy_write(dev, 0x0e, reg); in mmd_write_reg()
47 phy_write(dev, 0x0d, (1 << 14) | device); in mmd_write_reg()
48 phy_write(dev, 0x0e, val); in mmd_write_reg()
97 phy_write(dev, 0xd, 0x7); in ar8031_phy_fixup()
[all …]
H A Dmach-imx7d.c22 phy_write(dev, 0x1d, 0x1f); in ar8031_phy_fixup()
23 phy_write(dev, 0x1e, 0x8); in ar8031_phy_fixup()
26 phy_write(dev, 0xd, 0x3); in ar8031_phy_fixup()
27 phy_write(dev, 0xe, 0x805d); in ar8031_phy_fixup()
28 phy_write(dev, 0xd, 0x4003); in ar8031_phy_fixup()
31 phy_write(dev, 0xe, val); in ar8031_phy_fixup()
39 phy_write(dev, 0x1e, 0x21); in bcm54220_phy_fixup()
40 phy_write(dev, 0x1f, 0x7ea8); in bcm54220_phy_fixup()
41 phy_write(dev, 0x1e, 0x2f); in bcm54220_phy_fixup()
42 phy_write(dev, 0x1f, 0x71b7); in bcm54220_phy_fixup()
/OK3568_Linux_fs/kernel/drivers/net/ethernet/ibm/emac/
H A Dphy.c33 #define phy_write _phy_write macro
63 phy_write(phy, MII_BMCR, val); in emac_mii_reset_phy()
74 phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE); in emac_mii_reset_phy()
126 phy_write(phy, MII_BMCR, ctl); in genmii_setup_aneg()
146 phy_write(phy, MII_ADVERTISE, adv); in genmii_setup_aneg()
158 phy_write(phy, MII_CTRL1000, adv); in genmii_setup_aneg()
164 phy_write(phy, MII_BMCR, ctl); in genmii_setup_aneg()
184 phy_write(phy, MII_BMCR, ctl | BMCR_RESET); in genmii_setup_forced()
201 phy_write(phy, MII_BMCR, ctl); in genmii_setup_forced()
331 phy_write(phy, MII_CIS8201_EPCR, epcr); in cis8201_init()
[all …]
/OK3568_Linux_fs/kernel/drivers/phy/freescale/
H A Dphy-fsl-imx8-mipi-dphy.c110 static int phy_write(struct phy *phy, u32 value, unsigned int reg) in phy_write() function
292 phy_write(phy, priv->cfg.m_prg_hs_prepare, DPHY_M_PRG_HS_PREPARE); in mixel_phy_set_hs_timings()
293 phy_write(phy, priv->cfg.mc_prg_hs_prepare, DPHY_MC_PRG_HS_PREPARE); in mixel_phy_set_hs_timings()
294 phy_write(phy, priv->cfg.m_prg_hs_zero, DPHY_M_PRG_HS_ZERO); in mixel_phy_set_hs_timings()
295 phy_write(phy, priv->cfg.mc_prg_hs_zero, DPHY_MC_PRG_HS_ZERO); in mixel_phy_set_hs_timings()
296 phy_write(phy, priv->cfg.m_prg_hs_trail, DPHY_M_PRG_HS_TRAIL); in mixel_phy_set_hs_timings()
297 phy_write(phy, priv->cfg.mc_prg_hs_trail, DPHY_MC_PRG_HS_TRAIL); in mixel_phy_set_hs_timings()
298 phy_write(phy, priv->cfg.rxhs_settle, priv->devdata->reg_rxhs_settle); in mixel_phy_set_hs_timings()
314 phy_write(phy, CM(priv->cfg.cm), DPHY_CM); in mixel_dphy_set_pll_params()
315 phy_write(phy, CN(priv->cfg.cn), DPHY_CN); in mixel_dphy_set_pll_params()
[all …]
/OK3568_Linux_fs/u-boot/board/spear/x600/
H A Dx600.c84 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00); in board_phy_config()
111 phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020); in board_phy_config()
117 phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001); in board_phy_config()
120 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); in board_phy_config()
121 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); in board_phy_config()
124 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea); in board_phy_config()
127 phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000); in board_phy_config()
130 phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049); in board_phy_config()
/OK3568_Linux_fs/u-boot/board/congatec/cgtqmx6eval/
H A Dcgtqmx6eval.c336 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2); in mx6_rgmii_rework()
337 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 4); in mx6_rgmii_rework()
338 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2); in mx6_rgmii_rework()
339 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 0x0000); in mx6_rgmii_rework()
341 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2); in mx6_rgmii_rework()
342 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 5); in mx6_rgmii_rework()
343 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, MII_KSZ9031_MOD_DATA_POST_INC_W | 0x2); in mx6_rgmii_rework()
344 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, MII_KSZ9031_MOD_REG); in mx6_rgmii_rework()
346 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_CONTROL, 2); in mx6_rgmii_rework()
347 phy_write(phydev, MDIO_DEVAD_NONE, MMD_ACCESS_REG_DATA, 6); in mx6_rgmii_rework()
[all …]
/OK3568_Linux_fs/u-boot/board/Marvell/db-mv784mp-gp/
H A Ddb-mv784mp-gp.c96 phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 4); in board_phy_config()
98 phy_write(phydev, MDIO_DEVAD_NONE, 0x0, 0x1140); in board_phy_config()
100 phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0); in board_phy_config()
105 phy_write(phydev, MDIO_DEVAD_NONE, 0x4, reg); in board_phy_config()
108 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000); in board_phy_config()
109 phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140); in board_phy_config()
114 phy_write(phydev, MDIO_DEVAD_NONE, ETH_PHY_CTRL_REG, reg); in board_phy_config()

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