120 	phy_write(phydev, REG_PAGE_SEL, 0x0000);  in rk630_phy_wol_enable()
121 	phy_write(phydev, REG_MAC_ADDRESS0, ((u16)ndev->dev_addr[0] << 8) + ndev->dev_addr[1]);  in rk630_phy_wol_enable()
122 	phy_write(phydev, REG_MAC_ADDRESS1, ((u16)ndev->dev_addr[2] << 8) + ndev->dev_addr[3]);  in rk630_phy_wol_enable()
123 	phy_write(phydev, REG_MAC_ADDRESS2, ((u16)ndev->dev_addr[4] << 8) + ndev->dev_addr[5]);  in rk630_phy_wol_enable()
129 	phy_write(phydev, REG_GLOBAL_CONFIGURATION, value);  in rk630_phy_wol_enable()
133 	phy_write(phydev, REG_INTERRUPT_MASK, value);  in rk630_phy_wol_enable()
141 	phy_write(phydev, REG_PAGE_SEL, 0x0000);  in rk630_phy_wol_disable()
144 	phy_write(phydev, REG_GLOBAL_CONFIGURATION, value);  in rk630_phy_wol_disable()
152 	phy_write(phydev, REG_PAGE_SEL, 0x0100);  in rk630_phy_ieee_set()
158 	phy_write(phydev, REG_PAGE1_EEE_CONFIGURE, value);  in rk630_phy_ieee_set()
160 	phy_write(phydev, REG_PAGE_SEL, 0x0000);  in rk630_phy_ieee_set()
168 	phy_write(phydev, REG_PAGE_SEL, 0x0100);  in rk630_phy_set_aps()
174 	phy_write(phydev, REG_PAGE1_APS_CTRL, value);  in rk630_phy_set_aps()
176 	phy_write(phydev, REG_PAGE_SEL, 0x0000);  in rk630_phy_set_aps()
184 	phy_write(phydev, REG_PAGE_SEL, 0x0100);  in rk630_phy_set_uaps()
190 	phy_write(phydev, REG_PAGE1_UAPS_CONFIGURE, value);  in rk630_phy_set_uaps()
192 	phy_write(phydev, REG_PAGE_SEL, 0x0000);  in rk630_phy_set_uaps()
197 	phy_write(phydev, 0, phy_read(phydev, 0) & ~BIT(13));  in rk630_phy_s40_config_init()
200 	phy_write(phydev, REG_PAGE_SEL, 0x0100);  in rk630_phy_s40_config_init()
202 	phy_write(phydev, REG_PAGE1_APS_CTRL, 0x4824);  in rk630_phy_s40_config_init()
204 	phy_write(phydev, REG_PAGE_SEL, 0x0200);  in rk630_phy_s40_config_init()
206 	phy_write(phydev, REG_PAGE2_AFE_CTRL, 0x0000);  in rk630_phy_s40_config_init()
208 	phy_write(phydev, REG_PAGE_SEL, 0x0600);  in rk630_phy_s40_config_init()
210 	phy_write(phydev, REG_PAGE6_AFE_TX_CTRL, 0x708f);  in rk630_phy_s40_config_init()
212 	phy_write(phydev, REG_PAGE6_AFE_RX_CTRL, 0xf000);  in rk630_phy_s40_config_init()
213 	phy_write(phydev, REG_PAGE6_AFE_DRIVER2, 0x1530);  in rk630_phy_s40_config_init()
216 	phy_write(phydev, REG_PAGE_SEL, 0x0800);  in rk630_phy_s40_config_init()
218 	phy_write(phydev, REG_PAGE8_AFE_CTRL, 0x00bc);  in rk630_phy_s40_config_init()
221 	phy_write(phydev, REG_PAGE_SEL, 0x0000);  in rk630_phy_s40_config_init()
229 	phy_write(phydev, REG_PAGE_SEL, 0x0100);  in rk630_phy_t22_config_init()
231 	phy_write(phydev, 0x10, 0xfbfe);  in rk630_phy_t22_config_init()
233 	phy_write(phydev, REG_PAGE1_APS_CTRL, 0x4824);  in rk630_phy_t22_config_init()
235 	phy_write(phydev, REG_PAGE_SEL, 0x0200);  in rk630_phy_t22_config_init()
237 	phy_write(phydev, REG_PAGE2_AFE_CTRL, 0x0000);  in rk630_phy_t22_config_init()
239 	phy_write(phydev, REG_PAGE_SEL, 0x0600);  in rk630_phy_t22_config_init()
241 	phy_write(phydev, REG_PAGE6_ADC_ANONTROL, 0x555e);  in rk630_phy_t22_config_init()
243 	phy_write(phydev, REG_PAGE6_GAIN_ANONTROL, 0x0400);  in rk630_phy_t22_config_init()
245 	phy_write(phydev, REG_PAGE6_AFE_TX_CTRL, 0x1088);  in rk630_phy_t22_config_init()
251 	phy_write(phydev, REG_PAGE6_AFE_DRIVER2,  in rk630_phy_t22_config_init()
254 	phy_write(phydev, REG_PAGE6_CP_CURRENT, 0x0575);  in rk630_phy_t22_config_init()
256 	phy_write(phydev, REG_PAGE6_ADC_OP_BIAS, 0x0000);  in rk630_phy_t22_config_init()
258 	phy_write(phydev, REG_PAGE6_RX_DECTOR, 0x0408);  in rk630_phy_t22_config_init()
260 	phy_write(phydev, REG_PAGE6_AFE_PDCW, 0x8880);  in rk630_phy_t22_config_init()
262 	phy_write(phydev, REG_PAGE6_TX_MOS_DRV, 0x888e);  in rk630_phy_t22_config_init()
265 	phy_write(phydev, REG_PAGE_SEL, 0x0800);  in rk630_phy_t22_config_init()
267 	phy_write(phydev, REG_PAGE8_AUTO_CAL, 0x0844);  in rk630_phy_t22_config_init()
269 	phy_write(phydev, 0x13, 0xc096);  in rk630_phy_t22_config_init()
272 	phy_write(phydev, REG_PAGE_SEL, 0x0000);  in rk630_phy_t22_config_init()
275 	phy_write(phydev, REG_MMD_ACCESS_CONTROL, 0x0007);  in rk630_phy_t22_config_init()
276 	phy_write(phydev, REG_MMD_ACCESS_DATA_ADDRESS, 0x003c);  in rk630_phy_t22_config_init()
277 	phy_write(phydev, REG_MMD_ACCESS_CONTROL, 0x4007);  in rk630_phy_t22_config_init()
278 	phy_write(phydev, REG_MMD_ACCESS_DATA_ADDRESS, 0x0000);  in rk630_phy_t22_config_init()
314 		phy_write(phydev, REG_PAGE_SEL, 0x0600);  in rk630_link_change_notify()
319 		phy_write(phydev, REG_PAGE6_AFE_TX_CTRL, val);  in rk630_link_change_notify()
321 		phy_write(phydev, REG_PAGE_SEL, 0x0000);  in rk630_link_change_notify()
329 	phy_write(priv->phydev, REG_INTERRUPT_STATUS, BIT(14));  in rk630_wol_irq_thread()
384 		phy_write(phydev, REG_INTERRUPT_MASK, BIT(14));  in rk630_phy_suspend()
396 		phy_write(phydev, REG_INTERRUPT_MASK, 0);  in rk630_phy_resume()