1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2015 Freescale Semiconductor, Inc.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun #include <linux/irqchip.h>
6*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
7*4882a593Smuzhiyun #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
8*4882a593Smuzhiyun #include <linux/of_platform.h>
9*4882a593Smuzhiyun #include <linux/phy.h>
10*4882a593Smuzhiyun #include <linux/regmap.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <asm/mach/arch.h>
13*4882a593Smuzhiyun #include <asm/mach/map.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include "common.h"
16*4882a593Smuzhiyun
ar8031_phy_fixup(struct phy_device * dev)17*4882a593Smuzhiyun static int ar8031_phy_fixup(struct phy_device *dev)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun u16 val;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /* Set RGMII IO voltage to 1.8V */
22*4882a593Smuzhiyun phy_write(dev, 0x1d, 0x1f);
23*4882a593Smuzhiyun phy_write(dev, 0x1e, 0x8);
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /* disable phy AR8031 SmartEEE function. */
26*4882a593Smuzhiyun phy_write(dev, 0xd, 0x3);
27*4882a593Smuzhiyun phy_write(dev, 0xe, 0x805d);
28*4882a593Smuzhiyun phy_write(dev, 0xd, 0x4003);
29*4882a593Smuzhiyun val = phy_read(dev, 0xe);
30*4882a593Smuzhiyun val &= ~(0x1 << 8);
31*4882a593Smuzhiyun phy_write(dev, 0xe, val);
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun return 0;
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun
bcm54220_phy_fixup(struct phy_device * dev)36*4882a593Smuzhiyun static int bcm54220_phy_fixup(struct phy_device *dev)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun /* enable RXC skew select RGMII copper mode */
39*4882a593Smuzhiyun phy_write(dev, 0x1e, 0x21);
40*4882a593Smuzhiyun phy_write(dev, 0x1f, 0x7ea8);
41*4882a593Smuzhiyun phy_write(dev, 0x1e, 0x2f);
42*4882a593Smuzhiyun phy_write(dev, 0x1f, 0x71b7);
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun return 0;
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun #define PHY_ID_AR8031 0x004dd074
48*4882a593Smuzhiyun #define PHY_ID_BCM54220 0x600d8589
49*4882a593Smuzhiyun
imx7d_enet_phy_init(void)50*4882a593Smuzhiyun static void __init imx7d_enet_phy_init(void)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun if (IS_BUILTIN(CONFIG_PHYLIB)) {
53*4882a593Smuzhiyun phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
54*4882a593Smuzhiyun ar8031_phy_fixup);
55*4882a593Smuzhiyun phy_register_fixup_for_uid(PHY_ID_BCM54220, 0xffffffff,
56*4882a593Smuzhiyun bcm54220_phy_fixup);
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
imx7d_enet_clk_sel(void)60*4882a593Smuzhiyun static void __init imx7d_enet_clk_sel(void)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun struct regmap *gpr;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun gpr = syscon_regmap_lookup_by_compatible("fsl,imx7d-iomuxc-gpr");
65*4882a593Smuzhiyun if (!IS_ERR(gpr)) {
66*4882a593Smuzhiyun regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_TX_CLK_SEL_MASK, 0);
67*4882a593Smuzhiyun regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_CLK_DIR_MASK, 0);
68*4882a593Smuzhiyun } else {
69*4882a593Smuzhiyun pr_err("failed to find fsl,imx7d-iomux-gpr regmap\n");
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
imx7d_enet_init(void)73*4882a593Smuzhiyun static inline void imx7d_enet_init(void)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun imx7d_enet_phy_init();
76*4882a593Smuzhiyun imx7d_enet_clk_sel();
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
imx7d_init_machine(void)79*4882a593Smuzhiyun static void __init imx7d_init_machine(void)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun imx_anatop_init();
82*4882a593Smuzhiyun imx7d_enet_init();
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
imx7d_init_late(void)85*4882a593Smuzhiyun static void __init imx7d_init_late(void)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun if (IS_ENABLED(CONFIG_ARM_IMX_CPUFREQ_DT))
88*4882a593Smuzhiyun platform_device_register_simple("imx-cpufreq-dt", -1, NULL, 0);
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
imx7d_init_irq(void)91*4882a593Smuzhiyun static void __init imx7d_init_irq(void)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun imx_init_revision_from_anatop();
94*4882a593Smuzhiyun imx_src_init();
95*4882a593Smuzhiyun irqchip_init();
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun static const char *const imx7d_dt_compat[] __initconst = {
99*4882a593Smuzhiyun "fsl,imx7d",
100*4882a593Smuzhiyun "fsl,imx7s",
101*4882a593Smuzhiyun NULL,
102*4882a593Smuzhiyun };
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual (Device Tree)")
105*4882a593Smuzhiyun .init_irq = imx7d_init_irq,
106*4882a593Smuzhiyun .init_machine = imx7d_init_machine,
107*4882a593Smuzhiyun .init_late = imx7d_init_late,
108*4882a593Smuzhiyun .dt_compat = imx7d_dt_compat,
109*4882a593Smuzhiyun MACHINE_END
110