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Searched refs:cfgr (Results 1 – 17 of 17) sorted by relevance

/OK3568_Linux_fs/u-boot/arch/arm/mach-stm32/stm32f4/
H A Dclock.c146 writel(0, &STM32_RCC->cfgr); /* Reset CFGR */ in configure_clocks()
162 setbits_le32(&STM32_RCC->cfgr, (( in configure_clocks()
180 clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1)); in configure_clocks()
181 setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL); in configure_clocks()
183 while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) != in configure_clocks()
202 if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) == in clock_get()
219 (readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK) in clock_get()
225 (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK) in clock_get()
231 (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK) in clock_get()
/OK3568_Linux_fs/u-boot/drivers/clk/
H A Dclk_stm32f7.c120 writel(0, &regs->cfgr); /* Reset CFGR */ in configure_clocks()
132 setbits_le32(&regs->cfgr, (( in configure_clocks()
164 clrbits_le32(&regs->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1)); in configure_clocks()
165 setbits_le32(&regs->cfgr, RCC_CFGR_SW_PLL); in configure_clocks()
167 while ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) != in configure_clocks()
188 if ((readl(&regs->cfgr) & RCC_CFGR_SWS_MASK) == in stm32_clk_get_rate()
208 (readl(&regs->cfgr) & RCC_CFGR_AHB_PSC_MASK) in stm32_clk_get_rate()
215 (readl(&regs->cfgr) & RCC_CFGR_APB1_PSC_MASK) in stm32_clk_get_rate()
222 (readl(&regs->cfgr) & RCC_CFGR_APB2_PSC_MASK) in stm32_clk_get_rate()
/OK3568_Linux_fs/u-boot/drivers/gpio/
H A Datmel_pio4.c64 writel(reg, &port_base->cfgr); in atmel_pio4_config_io_func()
141 writel(reg, &port_base->cfgr); in atmel_pio4_set_pio_output()
167 writel(reg, &port_base->cfgr); in atmel_pio4_get_pio_input()
202 clrbits_le32(&port_base->cfgr, in atmel_pio4_direction_input()
218 clrsetbits_le32(&port_base->cfgr, in atmel_pio4_direction_output()
264 return (readl(&port_base->cfgr) & in atmel_pio4_get_function()
/OK3568_Linux_fs/kernel/drivers/mmc/host/
H A Dmmci_stm32_sdmmc.c374 u32 cfgr; in sdmmc_dlyb_set_cfgr() local
378 cfgr = FIELD_PREP(DLYB_CFGR_UNIT_MASK, unit) | in sdmmc_dlyb_set_cfgr()
380 writel_relaxed(cfgr, dlyb->base + DLYB_CFGR); in sdmmc_dlyb_set_cfgr()
389 u32 cfgr; in sdmmc_dlyb_lng_tuning() local
395 ret = readl_relaxed_poll_timeout(dlyb->base + DLYB_CFGR, cfgr, in sdmmc_dlyb_lng_tuning()
396 (cfgr & DLYB_CFGR_LNGF), in sdmmc_dlyb_lng_tuning()
401 i, cfgr); in sdmmc_dlyb_lng_tuning()
405 lng = FIELD_GET(DLYB_CFGR_LNG_MASK, cfgr); in sdmmc_dlyb_lng_tuning()
/OK3568_Linux_fs/kernel/drivers/pwm/
H A Dpwm-stm32-lp.c40 u32 val, mask, cfgr, presc = 0; in stm32_pwm_lp_apply() local
90 ret = regmap_read(priv->regmap, STM32_LPTIM_CFGR, &cfgr); in stm32_pwm_lp_apply()
94 if ((FIELD_GET(STM32_LPTIM_PRESC, cfgr) != presc) || in stm32_pwm_lp_apply()
95 (FIELD_GET(STM32_LPTIM_WAVPOL, cfgr) != state->polarity)) { in stm32_pwm_lp_apply()
/OK3568_Linux_fs/kernel/sound/soc/stm/
H A Dstm32_i2s.c507 u32 cfgr, cfgr_mask, cfg1; in stm32_i2s_configure() local
513 cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_16); in stm32_i2s_configure()
517 cfgr = I2S_CGFR_DATLEN_SET(I2S_I2SMOD_DATLEN_32) | in stm32_i2s_configure()
527 cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_SLAVE); in stm32_i2s_configure()
530 cfgr |= I2S_CGFR_FIXCH; in stm32_i2s_configure()
533 cfgr |= I2S_CGFR_I2SCFG_SET(I2S_I2SMOD_FD_MASTER); in stm32_i2s_configure()
538 cfgr_mask, cfgr); in stm32_i2s_configure()
/OK3568_Linux_fs/kernel/drivers/perf/
H A Darm_smmuv3_pmu.c733 u32 cfgr, reg_size; in smmu_pmu_probe() local
765 cfgr = readl_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CFGR); in smmu_pmu_probe()
768 if (cfgr & SMMU_PMCG_CFGR_RELOC_CTRS) { in smmu_pmu_probe()
785 smmu_pmu->num_counters = FIELD_GET(SMMU_PMCG_CFGR_NCTR, cfgr) + 1; in smmu_pmu_probe()
787 smmu_pmu->global_filter = !!(cfgr & SMMU_PMCG_CFGR_SID_FILTER_TYPE); in smmu_pmu_probe()
789 reg_size = FIELD_GET(SMMU_PMCG_CFGR_SIZE, cfgr); in smmu_pmu_probe()
/OK3568_Linux_fs/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91_mc.h21 u32 cfgr; /* 0x04 Configuration Register */ member
H A Datmel_pio4.h15 u32 cfgr; /* 0x04 PIO Configuration Register */ member
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-stm32f4/
H A Dstm32.h43 u32 cfgr; /* RCC clock configuration */ member
/OK3568_Linux_fs/kernel/drivers/net/ethernet/freescale/enetc/
H A Denetc_pf.c377 u32 cfgr; in enetc_pf_set_vf_spoofchk() local
382 cfgr = enetc_port_rd(&priv->si->hw, ENETC_PSICFGR0(vf + 1)); in enetc_pf_set_vf_spoofchk()
383 cfgr = (cfgr & ~ENETC_PSICFGR0_ASE) | (en ? ENETC_PSICFGR0_ASE : 0); in enetc_pf_set_vf_spoofchk()
384 enetc_port_wr(&priv->si->hw, ENETC_PSICFGR0(vf + 1), cfgr); in enetc_pf_set_vf_spoofchk()
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/dma/
H A Dsnps,dw-axi-dmac.txt29 clock-names = "core-clk", "cfgr-clk";
/OK3568_Linux_fs/u-boot/drivers/pinctrl/
H A Dpinctrl-at91-pio4.c145 writel(conf, &bank_base->cfgr); in atmel_pinctrl_set_state()
/OK3568_Linux_fs/kernel/drivers/pinctrl/
H A Dpinctrl-at91-pio4.c130 u32 cfgr[ATMEL_PIO_NPINS_PER_BANK]; member
944 atmel_pioctrl->pm_suspend_backup[i].cfgr[j] = in atmel_pctrl_suspend()
967 atmel_pioctrl->pm_suspend_backup[i].cfgr[j]); in atmel_pctrl_resume()
/OK3568_Linux_fs/kernel/arch/arc/boot/dts/
H A Dhsdk.dts333 clock-names = "core-clk", "cfgr-clk";
/OK3568_Linux_fs/kernel/drivers/net/ethernet/freescale/
H A Dfec_main.c1044 u32 cfgr; in fec_restart() local
1055 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII) in fec_restart()
1058 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M; in fec_restart()
1059 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); in fec_restart()
/OK3568_Linux_fs/kernel/drivers/net/wireless/cisco/
H A Dairo.c1829 ConfigRid cfgr; in writeConfigRid() local
1837 cfgr = ai->config; in writeConfigRid()
1839 if ((cfgr.opmode & MODE_CFG_MASK) == MODE_STA_IBSS) in writeConfigRid()
1844 return PC4500_writerid(ai, RID_CONFIG, &cfgr, sizeof(cfgr), lock); in writeConfigRid()