xref: /OK3568_Linux_fs/u-boot/drivers/pinctrl/pinctrl-at91-pio4.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Atmel PIO4 pinctrl driver
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Copyright (C) 2016 Atmel Corporation
5*4882a593Smuzhiyun  *               Wenyou.Yang <wenyou.yang@atmel.com>
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <dm.h>
12*4882a593Smuzhiyun #include <dm/pinctrl.h>
13*4882a593Smuzhiyun #include <linux/io.h>
14*4882a593Smuzhiyun #include <linux/err.h>
15*4882a593Smuzhiyun #include <mach/atmel_pio4.h>
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun /*
20*4882a593Smuzhiyun  * Warning:
21*4882a593Smuzhiyun  * In order to not introduce confusion between Atmel PIO groups and pinctrl
22*4882a593Smuzhiyun  * framework groups, Atmel PIO groups will be called banks.
23*4882a593Smuzhiyun  */
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun struct atmel_pio4_platdata {
26*4882a593Smuzhiyun 	struct atmel_pio4_port *reg_base;
27*4882a593Smuzhiyun };
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun static const struct pinconf_param conf_params[] = {
30*4882a593Smuzhiyun 	{ "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
31*4882a593Smuzhiyun 	{ "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
32*4882a593Smuzhiyun 	{ "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
33*4882a593Smuzhiyun 	{ "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 },
34*4882a593Smuzhiyun 	{ "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
35*4882a593Smuzhiyun 	{ "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
36*4882a593Smuzhiyun 	{ "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 },
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun 
atmel_pinctrl_get_pinconf(const void * blob,int node)39*4882a593Smuzhiyun static u32 atmel_pinctrl_get_pinconf(const void *blob, int node)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun 	const struct pinconf_param *params;
42*4882a593Smuzhiyun 	u32 param, arg, conf = 0;
43*4882a593Smuzhiyun 	u32 i;
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(conf_params); i++) {
46*4882a593Smuzhiyun 		params = &conf_params[i];
47*4882a593Smuzhiyun 		if (!fdt_get_property(blob, node, params->property, NULL))
48*4882a593Smuzhiyun 			continue;
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun 		param = params->param;
51*4882a593Smuzhiyun 		arg = params->default_value;
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun 		switch (param) {
54*4882a593Smuzhiyun 		case PIN_CONFIG_BIAS_DISABLE:
55*4882a593Smuzhiyun 			conf &= (~ATMEL_PIO_PUEN_MASK);
56*4882a593Smuzhiyun 			conf &= (~ATMEL_PIO_PDEN_MASK);
57*4882a593Smuzhiyun 			break;
58*4882a593Smuzhiyun 		case PIN_CONFIG_BIAS_PULL_UP:
59*4882a593Smuzhiyun 			conf |= ATMEL_PIO_PUEN_MASK;
60*4882a593Smuzhiyun 			break;
61*4882a593Smuzhiyun 		case PIN_CONFIG_BIAS_PULL_DOWN:
62*4882a593Smuzhiyun 			conf |= ATMEL_PIO_PDEN_MASK;
63*4882a593Smuzhiyun 			break;
64*4882a593Smuzhiyun 		case PIN_CONFIG_DRIVE_OPEN_DRAIN:
65*4882a593Smuzhiyun 			if (arg == 0)
66*4882a593Smuzhiyun 				conf &= (~ATMEL_PIO_OPD_MASK);
67*4882a593Smuzhiyun 			else
68*4882a593Smuzhiyun 				conf |= ATMEL_PIO_OPD_MASK;
69*4882a593Smuzhiyun 			break;
70*4882a593Smuzhiyun 		case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
71*4882a593Smuzhiyun 			if (arg == 0)
72*4882a593Smuzhiyun 				conf |= ATMEL_PIO_SCHMITT_MASK;
73*4882a593Smuzhiyun 			else
74*4882a593Smuzhiyun 				conf &= (~ATMEL_PIO_SCHMITT_MASK);
75*4882a593Smuzhiyun 			break;
76*4882a593Smuzhiyun 		case PIN_CONFIG_INPUT_DEBOUNCE:
77*4882a593Smuzhiyun 			if (arg == 0) {
78*4882a593Smuzhiyun 				conf &= (~ATMEL_PIO_IFEN_MASK);
79*4882a593Smuzhiyun 				conf &= (~ATMEL_PIO_IFSCEN_MASK);
80*4882a593Smuzhiyun 			} else {
81*4882a593Smuzhiyun 				conf |= ATMEL_PIO_IFEN_MASK;
82*4882a593Smuzhiyun 				conf |= ATMEL_PIO_IFSCEN_MASK;
83*4882a593Smuzhiyun 			}
84*4882a593Smuzhiyun 			break;
85*4882a593Smuzhiyun 		default:
86*4882a593Smuzhiyun 			printf("%s: Unsupported configuration parameter: %u\n",
87*4882a593Smuzhiyun 			       __func__, param);
88*4882a593Smuzhiyun 			break;
89*4882a593Smuzhiyun 		}
90*4882a593Smuzhiyun 	}
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun 	return conf;
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun 
atmel_pio4_bank_base(struct udevice * dev,u32 bank)95*4882a593Smuzhiyun static inline struct atmel_pio4_port *atmel_pio4_bank_base(struct udevice *dev,
96*4882a593Smuzhiyun 							   u32 bank)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun 	struct atmel_pio4_platdata *plat = dev_get_platdata(dev);
99*4882a593Smuzhiyun 	struct atmel_pio4_port *bank_base =
100*4882a593Smuzhiyun 			(struct atmel_pio4_port *)((u32)plat->reg_base +
101*4882a593Smuzhiyun 			ATMEL_PIO_BANK_OFFSET * bank);
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun 	return bank_base;
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun #define MAX_PINMUX_ENTRIES	40
107*4882a593Smuzhiyun 
atmel_pinctrl_set_state(struct udevice * dev,struct udevice * config)108*4882a593Smuzhiyun static int atmel_pinctrl_set_state(struct udevice *dev, struct udevice *config)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun 	struct atmel_pio4_port *bank_base;
111*4882a593Smuzhiyun 	const void *blob = gd->fdt_blob;
112*4882a593Smuzhiyun 	int node = dev_of_offset(config);
113*4882a593Smuzhiyun 	u32 offset, func, bank, line;
114*4882a593Smuzhiyun 	u32 cells[MAX_PINMUX_ENTRIES];
115*4882a593Smuzhiyun 	u32 i, conf;
116*4882a593Smuzhiyun 	int count;
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	conf = atmel_pinctrl_get_pinconf(blob, node);
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	count = fdtdec_get_int_array_count(blob, node, "pinmux",
121*4882a593Smuzhiyun 					   cells, ARRAY_SIZE(cells));
122*4882a593Smuzhiyun 	if (count < 0) {
123*4882a593Smuzhiyun 		printf("%s: bad pinmux array %d\n", __func__, count);
124*4882a593Smuzhiyun 		return -EINVAL;
125*4882a593Smuzhiyun 	}
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun 	if (count > MAX_PINMUX_ENTRIES) {
128*4882a593Smuzhiyun 		printf("%s: unsupported pinmux array count %d\n",
129*4882a593Smuzhiyun 		       __func__, count);
130*4882a593Smuzhiyun 		return -EINVAL;
131*4882a593Smuzhiyun 	}
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 	for (i = 0 ; i < count; i++) {
134*4882a593Smuzhiyun 		offset = ATMEL_GET_PIN_NO(cells[i]);
135*4882a593Smuzhiyun 		func = ATMEL_GET_PIN_FUNC(cells[i]);
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 		bank = ATMEL_PIO_BANK(offset);
138*4882a593Smuzhiyun 		line = ATMEL_PIO_LINE(offset);
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 		bank_base = atmel_pio4_bank_base(dev, bank);
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 		writel(BIT(line), &bank_base->mskr);
143*4882a593Smuzhiyun 		conf &= (~ATMEL_PIO_CFGR_FUNC_MASK);
144*4882a593Smuzhiyun 		conf |= (func & ATMEL_PIO_CFGR_FUNC_MASK);
145*4882a593Smuzhiyun 		writel(conf, &bank_base->cfgr);
146*4882a593Smuzhiyun 	}
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun 	return 0;
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun const struct pinctrl_ops atmel_pinctrl_ops  = {
152*4882a593Smuzhiyun 	.set_state = atmel_pinctrl_set_state,
153*4882a593Smuzhiyun };
154*4882a593Smuzhiyun 
atmel_pinctrl_probe(struct udevice * dev)155*4882a593Smuzhiyun static int atmel_pinctrl_probe(struct udevice *dev)
156*4882a593Smuzhiyun {
157*4882a593Smuzhiyun 	struct atmel_pio4_platdata *plat = dev_get_platdata(dev);
158*4882a593Smuzhiyun 	fdt_addr_t addr_base;
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	dev = dev_get_parent(dev);
161*4882a593Smuzhiyun 	addr_base = devfdt_get_addr(dev);
162*4882a593Smuzhiyun 	if (addr_base == FDT_ADDR_T_NONE)
163*4882a593Smuzhiyun 		return -EINVAL;
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun 	plat->reg_base = (struct atmel_pio4_port *)addr_base;
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun 	return 0;
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun static const struct udevice_id atmel_pinctrl_match[] = {
171*4882a593Smuzhiyun 	{ .compatible = "atmel,sama5d2-pinctrl" },
172*4882a593Smuzhiyun 	{}
173*4882a593Smuzhiyun };
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun U_BOOT_DRIVER(atmel_pinctrl) = {
176*4882a593Smuzhiyun 	.name = "pinctrl_atmel_pio4",
177*4882a593Smuzhiyun 	.id = UCLASS_PINCTRL,
178*4882a593Smuzhiyun 	.of_match = atmel_pinctrl_match,
179*4882a593Smuzhiyun 	.probe = atmel_pinctrl_probe,
180*4882a593Smuzhiyun 	.platdata_auto_alloc_size = sizeof(struct atmel_pio4_platdata),
181*4882a593Smuzhiyun 	.ops = &atmel_pinctrl_ops,
182*4882a593Smuzhiyun };
183