1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2015 Atmel Corporation. 3*4882a593Smuzhiyun * Wenyou Yang <wenyou.yang@atmel.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __ATMEL_PIO4_H 9*4882a593Smuzhiyun #define __ATMEL_PIO4_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun struct atmel_pio4_port { 14*4882a593Smuzhiyun u32 mskr; /* 0x00 PIO Mask Register */ 15*4882a593Smuzhiyun u32 cfgr; /* 0x04 PIO Configuration Register */ 16*4882a593Smuzhiyun u32 pdsr; /* 0x08 PIO Pin Data Status Register */ 17*4882a593Smuzhiyun u32 locksr; /* 0x0C PIO Lock Status Register */ 18*4882a593Smuzhiyun u32 sodr; /* 0x10 PIO Set Output Data Register */ 19*4882a593Smuzhiyun u32 codr; /* 0x14 PIO Clear Output Data Register */ 20*4882a593Smuzhiyun u32 odsr; /* 0x18 PIO Output Data Status Register */ 21*4882a593Smuzhiyun u32 reserved0; 22*4882a593Smuzhiyun u32 ier; /* 0x20 PIO Interrupt Enable Register */ 23*4882a593Smuzhiyun u32 idr; /* 0x24 PIO Interrupt Disable Register */ 24*4882a593Smuzhiyun u32 imr; /* 0x28 PIO Interrupt Mask Register */ 25*4882a593Smuzhiyun u32 isr; /* 0x2C PIO Interrupt Status Register */ 26*4882a593Smuzhiyun u32 reserved1[3]; 27*4882a593Smuzhiyun u32 iofr; /* 0x3C PIO I/O Freeze Register */ 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #endif 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* 33*4882a593Smuzhiyun * PIO Configuration Register Fields 34*4882a593Smuzhiyun */ 35*4882a593Smuzhiyun #define ATMEL_PIO_CFGR_FUNC_MASK GENMASK(2, 0) 36*4882a593Smuzhiyun #define ATMEL_PIO_CFGR_FUNC_GPIO (0x0 << 0) 37*4882a593Smuzhiyun #define ATMEL_PIO_CFGR_FUNC_PERIPH_A (0x1 << 0) 38*4882a593Smuzhiyun #define ATMEL_PIO_CFGR_FUNC_PERIPH_B (0x2 << 0) 39*4882a593Smuzhiyun #define ATMEL_PIO_CFGR_FUNC_PERIPH_C (0x3 << 0) 40*4882a593Smuzhiyun #define ATMEL_PIO_CFGR_FUNC_PERIPH_D (0x4 << 0) 41*4882a593Smuzhiyun #define ATMEL_PIO_CFGR_FUNC_PERIPH_E (0x5 << 0) 42*4882a593Smuzhiyun #define ATMEL_PIO_CFGR_FUNC_PERIPH_F (0x6 << 0) 43*4882a593Smuzhiyun #define ATMEL_PIO_CFGR_FUNC_PERIPH_G (0x7 << 0) 44*4882a593Smuzhiyun #define ATMEL_PIO_DIR_MASK BIT(8) 45*4882a593Smuzhiyun #define ATMEL_PIO_PUEN_MASK BIT(9) 46*4882a593Smuzhiyun #define ATMEL_PIO_PDEN_MASK BIT(10) 47*4882a593Smuzhiyun #define ATMEL_PIO_IFEN_MASK BIT(12) 48*4882a593Smuzhiyun #define ATMEL_PIO_IFSCEN_MASK BIT(13) 49*4882a593Smuzhiyun #define ATMEL_PIO_OPD_MASK BIT(14) 50*4882a593Smuzhiyun #define ATMEL_PIO_SCHMITT_MASK BIT(15) 51*4882a593Smuzhiyun #define ATMEL_PIO_CFGR_EVTSEL_MASK GENMASK(26, 24) 52*4882a593Smuzhiyun #define ATMEL_PIO_CFGR_EVTSEL_FALLING (0 << 24) 53*4882a593Smuzhiyun #define ATMEL_PIO_CFGR_EVTSEL_RISING (1 << 24) 54*4882a593Smuzhiyun #define ATMEL_PIO_CFGR_EVTSEL_BOTH (2 << 24) 55*4882a593Smuzhiyun #define ATMEL_PIO_CFGR_EVTSEL_LOW (3 << 24) 56*4882a593Smuzhiyun #define ATMEL_PIO_CFGR_EVTSEL_HIGH (4 << 24) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define ATMEL_PIO_NPINS_PER_BANK 32 59*4882a593Smuzhiyun #define ATMEL_PIO_BANK(pin_id) (pin_id / ATMEL_PIO_NPINS_PER_BANK) 60*4882a593Smuzhiyun #define ATMEL_PIO_LINE(pin_id) (pin_id % ATMEL_PIO_NPINS_PER_BANK) 61*4882a593Smuzhiyun #define ATMEL_PIO_BANK_OFFSET 0x40 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define ATMEL_GET_PIN_NO(pinfunc) ((pinfunc) & 0xff) 64*4882a593Smuzhiyun #define ATMEL_GET_PIN_FUNC(pinfunc) ((pinfunc >> 16) & 0xf) 65*4882a593Smuzhiyun #define ATMEL_GET_PIN_IOSET(pinfunc) ((pinfunc >> 20) & 0xf) 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define AT91_PIO_PORTA 0x0 68*4882a593Smuzhiyun #define AT91_PIO_PORTB 0x1 69*4882a593Smuzhiyun #define AT91_PIO_PORTC 0x2 70*4882a593Smuzhiyun #define AT91_PIO_PORTD 0x3 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun int atmel_pio4_set_gpio(u32 port, u32 pin, u32 use_pullup); 73*4882a593Smuzhiyun int atmel_pio4_set_a_periph(u32 port, u32 pin, u32 use_pullup); 74*4882a593Smuzhiyun int atmel_pio4_set_b_periph(u32 port, u32 pin, u32 use_pullup); 75*4882a593Smuzhiyun int atmel_pio4_set_c_periph(u32 port, u32 pin, u32 use_pullup); 76*4882a593Smuzhiyun int atmel_pio4_set_d_periph(u32 port, u32 pin, u32 use_pullup); 77*4882a593Smuzhiyun int atmel_pio4_set_e_periph(u32 port, u32 pin, u32 use_pullup); 78*4882a593Smuzhiyun int atmel_pio4_set_f_periph(u32 port, u32 pin, u32 use_pullup); 79*4882a593Smuzhiyun int atmel_pio4_set_g_periph(u32 port, u32 pin, u32 use_pullup); 80*4882a593Smuzhiyun int atmel_pio4_set_pio_output(u32 port, u32 pin, u32 value); 81*4882a593Smuzhiyun int atmel_pio4_get_pio_input(u32 port, u32 pin); 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #endif 84