1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef AT91_MC_H 8*4882a593Smuzhiyun #define AT91_MC_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define AT91_ASM_MC_EBI_CSA (ATMEL_BASE_MC + 0x60) 11*4882a593Smuzhiyun #define AT91_ASM_MC_EBI_CFG (ATMEL_BASE_MC + 0x64) 12*4882a593Smuzhiyun #define AT91_ASM_MC_SMC_CSR0 (ATMEL_BASE_MC + 0x70) 13*4882a593Smuzhiyun #define AT91_ASM_MC_SDRAMC_MR (ATMEL_BASE_MC + 0x90) 14*4882a593Smuzhiyun #define AT91_ASM_MC_SDRAMC_TR (ATMEL_BASE_MC + 0x94) 15*4882a593Smuzhiyun #define AT91_ASM_MC_SDRAMC_CR (ATMEL_BASE_MC + 0x98) 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun typedef struct at91_ebi { 20*4882a593Smuzhiyun u32 csa; /* 0x00 Chip Select Assignment Register */ 21*4882a593Smuzhiyun u32 cfgr; /* 0x04 Configuration Register */ 22*4882a593Smuzhiyun u32 reserved[2]; 23*4882a593Smuzhiyun } at91_ebi_t; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define AT91_EBI_CSA_CS0A 0x0001 26*4882a593Smuzhiyun #define AT91_EBI_CSA_CS1A 0x0002 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define AT91_EBI_CSA_CS3A 0x0008 29*4882a593Smuzhiyun #define AT91_EBI_CSA_CS4A 0x0010 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun typedef struct at91_sdramc { 32*4882a593Smuzhiyun u32 mr; /* 0x00 SDRAMC Mode Register */ 33*4882a593Smuzhiyun u32 tr; /* 0x04 SDRAMC Refresh Timer Register */ 34*4882a593Smuzhiyun u32 cr; /* 0x08 SDRAMC Configuration Register */ 35*4882a593Smuzhiyun u32 ssr; /* 0x0C SDRAMC Self Refresh Register */ 36*4882a593Smuzhiyun u32 lpr; /* 0x10 SDRAMC Low Power Register */ 37*4882a593Smuzhiyun u32 ier; /* 0x14 SDRAMC Interrupt Enable Register */ 38*4882a593Smuzhiyun u32 idr; /* 0x18 SDRAMC Interrupt Disable Register */ 39*4882a593Smuzhiyun u32 imr; /* 0x1C SDRAMC Interrupt Mask Register */ 40*4882a593Smuzhiyun u32 icr; /* 0x20 SDRAMC Interrupt Status Register */ 41*4882a593Smuzhiyun u32 reserved[3]; 42*4882a593Smuzhiyun } at91_sdramc_t; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun typedef struct at91_smc { 45*4882a593Smuzhiyun u32 csr[8]; /* 0x00 SDRAMC Mode Register */ 46*4882a593Smuzhiyun } at91_smc_t; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define AT91_SMC_CSR_RWHOLD(x) ((x & 0x7) << 28) 49*4882a593Smuzhiyun #define AT91_SMC_CSR_RWSETUP(x) ((x & 0x7) << 24) 50*4882a593Smuzhiyun #define AT91_SMC_CSR_ACSS_STANDARD 0x00000000 51*4882a593Smuzhiyun #define AT91_SMC_CSR_ACSS_1CYCLE 0x00010000 52*4882a593Smuzhiyun #define AT91_SMC_CSR_ACSS_2CYCLE 0x00020000 53*4882a593Smuzhiyun #define AT91_SMC_CSR_ACSS_3CYCLE 0x00030000 54*4882a593Smuzhiyun #define AT91_SMC_CSR_DRP 0x00008000 55*4882a593Smuzhiyun #define AT91_SMC_CSR_DBW_8 0x00004000 56*4882a593Smuzhiyun #define AT91_SMC_CSR_DBW_16 0x00002000 57*4882a593Smuzhiyun #define AT91_SMC_CSR_BAT_8 0x00000000 58*4882a593Smuzhiyun #define AT91_SMC_CSR_BAT_16 0x00001000 59*4882a593Smuzhiyun #define AT91_SMC_CSR_TDF(x) ((x & 0xF) << 8) 60*4882a593Smuzhiyun #define AT91_SMC_CSR_WSEN 0x00000080 61*4882a593Smuzhiyun #define AT91_SMC_CSR_NWS(x) (x & 0x7F) 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun typedef struct at91_bfc { 64*4882a593Smuzhiyun u32 mr; /* 0x00 SDRAMC Mode Register */ 65*4882a593Smuzhiyun } at91_bfc_t; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun typedef struct at91_mc { 68*4882a593Smuzhiyun u32 rcr; /* 0x00 MC Remap Control Register */ 69*4882a593Smuzhiyun u32 asr; /* 0x04 MC Abort Status Register */ 70*4882a593Smuzhiyun u32 aasr; /* 0x08 MC Abort Address Status Reg */ 71*4882a593Smuzhiyun u32 mpr; /* 0x0C MC Master Priority Register */ 72*4882a593Smuzhiyun u32 reserved1[20]; /* 0x10-0x5C */ 73*4882a593Smuzhiyun at91_ebi_t ebi; /* 0x60 - 0x6C EBI */ 74*4882a593Smuzhiyun at91_smc_t smc; /* 0x70 - 0x8C SMC User Interface */ 75*4882a593Smuzhiyun at91_sdramc_t sdramc; /* 0x90 - 0xBC SDRAMC User Interface */ 76*4882a593Smuzhiyun at91_bfc_t bfc; /* 0xC0 BFC User Interface */ 77*4882a593Smuzhiyun u32 reserved2[15]; 78*4882a593Smuzhiyun } at91_mc_t; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #endif 81*4882a593Smuzhiyun #endif 82