1*4882a593SmuzhiyunSynopsys DesignWare AXI DMA Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: "snps,axi-dma-1.01a" 5*4882a593Smuzhiyun- reg: Address range of the DMAC registers. This should include 6*4882a593Smuzhiyun all of the per-channel registers. 7*4882a593Smuzhiyun- interrupt: Should contain the DMAC interrupt number. 8*4882a593Smuzhiyun- dma-channels: Number of channels supported by hardware. 9*4882a593Smuzhiyun- snps,dma-masters: Number of AXI masters supported by the hardware. 10*4882a593Smuzhiyun- snps,data-width: Maximum AXI data width supported by hardware. 11*4882a593Smuzhiyun (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits) 12*4882a593Smuzhiyun- snps,priority: Priority of channel. Array size is equal to the number of 13*4882a593Smuzhiyun dma-channels. Priority value must be programmed within [0:dma-channels-1] 14*4882a593Smuzhiyun range. (0 - minimum priority) 15*4882a593Smuzhiyun- snps,block-size: Maximum block size supported by the controller channel. 16*4882a593Smuzhiyun Array size is equal to the number of dma-channels. 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunOptional properties: 19*4882a593Smuzhiyun- snps,axi-max-burst-len: Restrict master AXI burst length by value specified 20*4882a593Smuzhiyun in this property. If this property is missing the maximum AXI burst length 21*4882a593Smuzhiyun supported by DMAC is used. [1:256] 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunExample: 24*4882a593Smuzhiyun 25*4882a593Smuzhiyundmac: dma-controller@80000 { 26*4882a593Smuzhiyun compatible = "snps,axi-dma-1.01a"; 27*4882a593Smuzhiyun reg = <0x80000 0x400>; 28*4882a593Smuzhiyun clocks = <&core_clk>, <&cfgr_clk>; 29*4882a593Smuzhiyun clock-names = "core-clk", "cfgr-clk"; 30*4882a593Smuzhiyun interrupt-parent = <&intc>; 31*4882a593Smuzhiyun interrupts = <27>; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun dma-channels = <4>; 34*4882a593Smuzhiyun snps,dma-masters = <2>; 35*4882a593Smuzhiyun snps,data-width = <3>; 36*4882a593Smuzhiyun snps,block-size = <4096 4096 4096 4096>; 37*4882a593Smuzhiyun snps,priority = <0 1 2 3>; 38*4882a593Smuzhiyun snps,axi-max-burst-len = <16>; 39*4882a593Smuzhiyun}; 40