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Searched refs:UPDATE (Results 1 – 25 of 84) sorted by relevance

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/OK3568_Linux_fs/kernel/drivers/media/i2c/rk628/
H A Drk628_hdmirx.h31 #define HOT_PLUG_DETECT_INPUT_A(x) UPDATE(x, 24, 24)
33 #define HOT_PLUG_DETECT(x) UPDATE(x, 0, 0)
38 #define SEL_PIXCLKSRC(x) UPDATE(x, 19, 18)
40 #define INPUT_SELECT(x) UPDATE(x, 16, 16)
46 #define SPIKE_FILTER_EN(x) UPDATE(x, 18, 18)
48 #define DVI_MODE_HYST(x) UPDATE(x, 17, 13)
50 #define HDMI_MODE_HYST(x) UPDATE(x, 12, 8)
52 #define HDMI_MODE(x) UPDATE(x, 7, 6)
54 #define GB_DET(x) UPDATE(x, 5, 4)
56 #define EESS_OESS(x) UPDATE(x, 3, 2)
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H A Drk628_dsi.h24 #define TO_CLK_DIVISION(x) UPDATE(x, 15, 8)
25 #define TX_ESC_CLK_DIVISION(x) UPDATE(x, 7, 0)
27 #define DPI_VID(x) UPDATE(x, 1, 0)
30 #define DPI_COLOR_CODING(x) UPDATE(x, 3, 0)
38 #define OUTVACT_LPCMD_TIME(x) UPDATE(x, 23, 16)
39 #define INVACT_LPCMD_TIME(x) UPDATE(x, 7, 0)
48 #define CMD_VIDEO_MODE(x) UPDATE(x, 0, 0)
59 #define VID_MODE_TYPE(x) UPDATE(x, 1, 0)
61 #define VID_PKT_SIZE(x) UPDATE(x, 13, 0)
65 #define VID_HSA_TIME(x) UPDATE(x, 11, 0)
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H A Drk628.h17 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) macro
22 #define SW_VSYNC_POL(x) UPDATE(x, 26, 26)
24 #define SW_HSYNC_POL(x) UPDATE(x, 25, 25)
26 #define SW_ADAPTER_I2CSLADR(x) UPDATE(x, 24, 22)
28 #define SW_EDID_MODE(x) UPDATE(x, 21, 21)
30 #define SW_I2S_DATA_OEN(x) UPDATE(x, 10, 10)
34 #define SW_EFUSE_HDCP_EN(x) UPDATE(x, 8, 8)
36 #define SW_OUTPUT_MODE(x) UPDATE(x, 7, 3)
38 #define SW_INPUT_MODE(x) UPDATE(x, 2, 0)
43 #define GRF_GPIO_RX_CEC_SEL(x) UPDATE(x, 7, 7)
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H A Drk628_csi.h19 #define VOP_YU_SWAP(x) UPDATE(x, 14, 14)
21 #define VOP_UV_SWAP(x) UPDATE(x, 13, 13)
23 #define VOP_YUV422_EN(x) UPDATE(x, 12, 12)
25 #define VOP_P2_EN(x) UPDATE(x, 8, 8)
27 #define LANE_NUM(x) UPDATE(x, 5, 4)
29 #define DPHY_EN(x) UPDATE(x, 2, 2)
31 #define CSITX_EN(x) UPDATE(x, 0, 0)
36 #define BYPASS_SELECT(x) UPDATE(x, 0, 0)
42 #define CONT_MODE_CLK_CLR(x) UPDATE(x, 8, 8)
44 #define CONT_MODE_CLK_SET(x) UPDATE(x, 4, 4)
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H A Drk628_combtxphy.h16 #define SW_TX_IDLE(x) UPDATE(x, 29, 20)
18 #define SW_TX_PD(x) UPDATE(x, 17, 8)
20 #define SW_BUS_WIDTH_7BIT UPDATE(0x3, 6, 5)
21 #define SW_BUS_WIDTH_8BIT UPDATE(0x2, 6, 5)
22 #define SW_BUS_WIDTH_9BIT UPDATE(0x1, 6, 5)
23 #define SW_BUS_WIDTH_10BIT UPDATE(0x0, 6, 5)
39 #define SW_RATE(x) UPDATE(x, 26, 24)
40 #define SW_REF_DIV(x) UPDATE(x, 20, 16)
41 #define SW_PLL_FB_DIV(x) UPDATE(x, 14, 10)
42 #define SW_PLL_FRAC_DIV(x) UPDATE(x, 9, 0)
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/OK3568_Linux_fs/kernel/drivers/misc/rk628/
H A Drk628_hdmitx.h30 #define NOT_RST_ANALOG(x) UPDATE(x, 6, 6)
32 #define NOT_RST_DIGITAL(x) UPDATE(x, 5, 5)
34 #define REG_CLK_INV(x) UPDATE(x, 4, 4)
36 #define VCLK_INV(x) UPDATE(x, 3, 3)
38 #define REG_CLK_SOURCE(x) UPDATE(x, 2, 2)
40 #define PWR_OFF(x) UPDATE(x, 1, 1)
42 #define INT_POL(x) UPDATE(x, 0, 0)
46 #define VIDEO_INPUT_SDR_RGB444 UPDATE(0x0, 3, 1)
47 #define VIDEO_INPUT_DDR_RGB444 UPDATE(0x5, 3, 1)
48 #define VIDEO_INPUT_DDR_YCBCR422 UPDATE(0x6, 3, 1)
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H A Drk628_hdmirx.h22 #define HOT_PLUG_DETECT(x) UPDATE(x, 0, 0)
37 #define SEL_PIXCLKSRC(x) UPDATE(x, 19, 18)
50 #define PREAMBLE_CNT_LIMIT(x) UPDATE(x, 31, 27)
52 #define OESSCTL3_THR(x) UPDATE(x, 20, 19)
54 #define SPIKE_FILTER_EN(x) UPDATE(x, 18, 18)
56 #define DVI_MODE_HYST(x) UPDATE(x, 17, 13)
58 #define HDMI_MODE_HYST(x) UPDATE(x, 12, 8)
60 #define HDMI_MODE(x) UPDATE(x, 7, 6)
62 #define GB_DET(x) UPDATE(x, 5, 4)
64 #define EESS_OESS(x) UPDATE(x, 3, 2)
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H A Drk628_dsi.h20 #define TO_CLK_DIVISION(x) UPDATE(x, 15, 8)
21 #define TX_ESC_CLK_DIVISION(x) UPDATE(x, 7, 0)
23 #define DPI_VID(x) UPDATE(x, 1, 0)
26 #define DPI_COLOR_CODING(x) UPDATE(x, 3, 0)
34 #define OUTVACT_LPCMD_TIME(x) UPDATE(x, 23, 16)
35 #define INVACT_LPCMD_TIME(x) UPDATE(x, 7, 0)
44 #define CMD_VIDEO_MODE(x) UPDATE(x, 0, 0)
55 #define VID_MODE_TYPE(x) UPDATE(x, 1, 0)
57 #define VID_PKT_SIZE(x) UPDATE(x, 13, 0)
61 #define VID_HSA_TIME(x) UPDATE(x, 11, 0)
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H A Drk628_csi.h20 #define VOP_YU_SWAP(x) UPDATE(x, 14, 14)
22 #define VOP_UV_SWAP(x) UPDATE(x, 13, 13)
24 #define VOP_YUV422_EN(x) UPDATE(x, 12, 12)
26 #define VOP_P2_EN(x) UPDATE(x, 8, 8)
28 #define LANE_NUM(x) UPDATE(x, 5, 4)
30 #define DPHY_EN(x) UPDATE(x, 2, 2)
32 #define CSITX_EN(x) UPDATE(x, 0, 0)
37 #define BYPASS_SELECT(x) UPDATE(x, 0, 0)
43 #define CONT_MODE_CLK_CLR(x) UPDATE(x, 8, 8)
45 #define CONT_MODE_CLK_SET(x) UPDATE(x, 4, 4)
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H A Drk628_gvi.h44 #define SYS_CTRL0_LANE_NUM(x) UPDATE(x, 7, 4)
46 #define SYS_CTRL0_BYTE_MODE(x) UPDATE(x, 9, 8)
48 #define SYS_CTRL0_SECTION_NUM(x) UPDATE(x, 11, 10)
58 #define SYS_CTRL0_GVI_GN_EN(x) UPDATE(x, 19, 16)
73 #define SYS_CTRL1_COLOR_DEPTH(x) UPDATE(x, 3, 0)
87 #define SYS_CTRL2_AFIFO_READ_THOLD(x) UPDATE(x, 7, 0)
89 #define SYS_CTRL2_AFIFO_ALMOST_FULL_THOLD(x) UPDATE(x, 23, 16)
91 #define SYS_CTRL2_AFIFO_ALMOST_EMPTY_THOLD(x) UPDATE(x, 31, 24)
95 #define SYS_CTRL3_LANE0_SEL(x) UPDATE(x, 2, 0)
97 #define SYS_CTRL3_LANE1_SEL(x) UPDATE(x, 6, 4)
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H A Drk628_combtxphy.h16 #define SW_TX_IDLE(x) UPDATE(x, 29, 20)
18 #define SW_TX_PD(x) UPDATE(x, 17, 8)
20 #define SW_BUS_WIDTH_7BIT UPDATE(0x3, 6, 5)
21 #define SW_BUS_WIDTH_8BIT UPDATE(0x2, 6, 5)
22 #define SW_BUS_WIDTH_9BIT UPDATE(0x1, 6, 5)
23 #define SW_BUS_WIDTH_10BIT UPDATE(0x0, 6, 5)
39 #define SW_RATE(x) UPDATE(x, 26, 24)
40 #define SW_REF_DIV(x) UPDATE(x, 20, 16)
41 #define SW_PLL_FB_DIV(x) UPDATE(x, 14, 10)
42 #define SW_PLL_FRAC_DIV(x) UPDATE(x, 9, 0)
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H A Drk628.h22 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) macro
28 #define SW_VSYNC_POL(x) UPDATE(x, 26, 26)
30 #define SW_HSYNC_POL(x) UPDATE(x, 25, 25)
32 #define SW_ADAPTER_I2CSLADR(x) UPDATE(x, 24, 22)
34 #define SW_EDID_MODE(x) UPDATE(x, 21, 21)
36 #define SW_I2S_DATA_OEN(x) UPDATE(x, 10, 10)
40 #define SW_EFUSE_HDCP_EN(x) UPDATE(x, 8, 8)
42 #define SW_OUTPUT_MODE(x) UPDATE(x, 7, 3)
44 #define SW_INPUT_MODE(x) UPDATE(x, 2, 0)
49 #define GRF_GPIO_RX_CEC_SEL(x) UPDATE(x, 7, 7)
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/OK3568_Linux_fs/kernel/include/linux/mfd/
H A Drk628.h19 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) macro
24 #define SW_VSYNC_POL(x) UPDATE(x, 26, 26)
26 #define SW_HSYNC_POL(x) UPDATE(x, 25, 25)
28 #define SW_ADAPTER_I2CSLADR(x) UPDATE(x, 24, 22)
30 #define SW_EDID_MODE(x) UPDATE(x, 21, 21)
32 #define SW_I2S_DATA_OEN(x) UPDATE(x, 10, 10)
36 #define SW_EFUSE_HDCP_EN(x) UPDATE(x, 8, 8)
38 #define SW_OUTPUT_MODE(x) UPDATE(x, 7, 3)
40 #define SW_INPUT_MODE(x) UPDATE(x, 2, 0)
45 #define GRF_GPIO_RX_CEC_SEL(x) UPDATE(x, 7, 7)
[all …]
/OK3568_Linux_fs/kernel/drivers/video/rockchip/vehicle/
H A Dvehicle_samsung_dcphy_common.h53 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) macro
61 #define I_MUX_SEL(x) UPDATE(x, 6, 5)
66 #define S(x) UPDATE(x, 10, 8)
68 #define P(x) UPDATE(x, 5, 0)
72 #define M(x) UPDATE(x, 9, 0)
75 #define MRR(x) UPDATE(x, 13, 8)
77 #define MFR(x) UPDATE(x, 7, 0)
85 #define PLL_LOCK_CNT(x) UPDATE(x, 15, 0)
87 #define PLL_STB_CNT(x) UPDATE(x, 15, 0)
95 #define T_PHY_READY(x) UPDATE(x, 15, 0)
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/rk628/
H A Drk628_hdmirx.c30 #define HOT_PLUG_DETECT(x) UPDATE(x, 0, 0)
45 #define SEL_PIXCLKSRC(x) UPDATE(x, 19, 18)
58 #define PREAMBLE_CNT_LIMIT(x) UPDATE(x, 31, 27)
60 #define OESSCTL3_THR(x) UPDATE(x, 20, 19)
62 #define SPIKE_FILTER_EN(x) UPDATE(x, 18, 18)
64 #define DVI_MODE_HYST(x) UPDATE(x, 17, 13)
66 #define HDMI_MODE_HYST(x) UPDATE(x, 12, 8)
68 #define HDMI_MODE(x) UPDATE(x, 7, 6)
70 #define GB_DET(x) UPDATE(x, 5, 4)
72 #define EESS_OESS(x) UPDATE(x, 3, 2)
[all …]
H A Drk628_hdmi.c46 #define NOT_RST_ANALOG(x) UPDATE(x, 6, 6)
48 #define NOT_RST_DIGITAL(x) UPDATE(x, 5, 5)
50 #define REG_CLK_INV(x) UPDATE(x, 4, 4)
52 #define VCLK_INV(x) UPDATE(x, 3, 3)
54 #define REG_CLK_SOURCE(x) UPDATE(x, 2, 2)
56 #define PWR_OFF(x) UPDATE(x, 1, 1)
58 #define INT_POL(x) UPDATE(x, 0, 0)
62 #define VIDEO_INPUT_SDR_RGB444 UPDATE(0x0, 3, 1)
63 #define VIDEO_INPUT_DDR_RGB444 UPDATE(0x5, 3, 1)
64 #define VIDEO_INPUT_DDR_YCBCR422 UPDATE(0x6, 3, 1)
[all …]
H A Drk628_gvi.c56 #define SYS_CTRL0_LANE_NUM(x) UPDATE(x, 7, 4)
58 #define SYS_CTRL0_BYTE_MODE(x) UPDATE(x, 9, 8)
60 #define SYS_CTRL0_SECTION_NUM(x) UPDATE(x, 11, 10)
70 #define SYS_CTRL0_GVI_GN_EN(x) UPDATE(x, 19, 16)
85 #define SYS_CTRL1_COLOR_DEPTH(x) UPDATE(x, 3, 0)
99 #define SYS_CTRL2_AFIFO_READ_THOLD(x) UPDATE(x, 7, 0)
101 #define SYS_CTRL2_AFIFO_ALMOST_FULL_THOLD(x) UPDATE(x, 23, 16)
103 #define SYS_CTRL2_AFIFO_ALMOST_EMPTY_THOLD(x) UPDATE(x, 31, 24)
107 #define SYS_CTRL3_LANE0_SEL(x) UPDATE(x, 2, 0)
109 #define SYS_CTRL3_LANE1_SEL(x) UPDATE(x, 6, 4)
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/ebc-dev/tcon/
H A Debc_tcon.c29 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) macro
59 #define DSP_HTOTAL(x) UPDATE(x, 27, 16)
60 #define DSP_HS_END(x) UPDATE(x, 7, 0)
61 #define DSP_HACT_END(x) UPDATE(x, 26, 16)
62 #define DSP_HACT_ST(x) UPDATE(x, 7, 0)
63 #define DSP_VTOTAL(x) UPDATE(x, 26, 16)
64 #define DSP_VS_END(x) UPDATE(x, 7, 0)
65 #define DSP_VACT_END(x) UPDATE(x, 26, 16)
66 #define DSP_VACT_ST(x) UPDATE(x, 7, 0)
67 #define DSP_HEIGHT(x) UPDATE(x, 26, 16)
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/OK3568_Linux_fs/kernel/drivers/media/platform/rockchip/hdmirx/
H A Drk_hdmirx.h13 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) macro
50 #define FREQ_TUNE_START_VAL(x) UPDATE(x, 9, 0)
96 #define TMDSQPCLK_STABLE_FREQ_MARGIN(x) UPDATE(x, 30, 16)
98 #define AUDCLK_STABLE_FREQ_MARGIN(x) UPDATE(x, 11, 9)
104 #define LDO_AFE_PROG(x) UPDATE(x, 24, 23)
109 #define REFFREQ_SEL(x) UPDATE(x, 11, 9)
118 #define PHYCREG_CR_PARA_SELECTION_MODE(x) UPDATE(x, 1, 0)
131 #define SCRAMB_EN_SEL_QST(x) UPDATE(x, 1, 0)
139 #define VS_CNT_THR_QST(x) UPDATE(x, 27, 20)
141 #define HS_POL_QST(x) UPDATE(x, 19, 18)
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/OK3568_Linux_fs/u-boot/drivers/video/rk_eink/
H A Drk_ebc_tcon.c35 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) macro
65 #define DSP_HTOTAL(x) UPDATE(x, 27, 16)
66 #define DSP_HS_END(x) UPDATE(x, 7, 0)
67 #define DSP_HACT_END(x) UPDATE(x, 26, 16)
68 #define DSP_HACT_ST(x) UPDATE(x, 7, 0)
69 #define DSP_VTOTAL(x) UPDATE(x, 26, 16)
70 #define DSP_VS_END(x) UPDATE(x, 7, 0)
71 #define DSP_VACT_END(x) UPDATE(x, 26, 16)
72 #define DSP_VACT_ST(x) UPDATE(x, 7, 0)
73 #define DSP_HEIGHT(x) UPDATE(x, 26, 16)
[all …]
/OK3568_Linux_fs/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-inno-hdmi.c24 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) macro
37 #define RK3228_AUTO_TERM_RES_CAL_SPEED_14_8(x) UPDATE(x, 6, 0)
39 #define RK3228_AUTO_TERM_RES_CAL_SPEED_7_0(x) UPDATE(x, 7, 0)
54 #define RK3228_PRE_PLL_FB_DIV_8(x) UPDATE((x) >> 8, 7, 7)
56 #define RK3228_PCLK_VCO_DIV_5(x) UPDATE(x, 5, 5)
58 #define RK3228_PRE_PLL_PRE_DIV(x) UPDATE(x, 4, 0)
60 #define RK3228_PRE_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0)
64 #define RK3228_PRE_PLL_PCLK_DIV_B(x) UPDATE(x, 6, 5)
66 #define RK3228_PRE_PLL_PCLK_DIV_A(x) UPDATE(x, 4, 0)
69 #define RK3228_PRE_PLL_PCLK_DIV_C(x) UPDATE(x, 6, 5)
[all …]
H A Dphy-rockchip-inno-mipi-dphy.c29 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) macro
54 #define POWER_WORK_ENABLE UPDATE(1, 1, 0)
55 #define POWER_WORK_DISABLE UPDATE(2, 1, 0)
68 #define REG_FBDIV_HI(x) UPDATE(x, 5, 5)
70 #define REG_PREDIV(x) UPDATE(x, 4, 0)
73 #define REG_FBDIV_LO(x) UPDATE(x, 7, 0)
76 #define CLK_LANE_SKEW_PHASE_SET(x) UPDATE(x, 2, 0)
79 #define LDO_OUTPUT_SET_HI(x) UPDATE(x, 7, 7)
81 #define LANE_3_SKEW_PHASE_SET(x) UPDATE(x, 6, 4)
83 #define LDO_OUTPUT_SET_LO(x) UPDATE(x, 3, 3)
[all …]
/OK3568_Linux_fs/u-boot/drivers/video/drm/
H A Drk618_dsi.c28 #define TO_CLK_DIVIDSION(x) UPDATE(x, 15, 8)
29 #define TX_ESC_CLK_DIVIDSION(x) UPDATE(x, 7, 0)
37 #define DPI_COLOR_CODING(x) UPDATE(x, 4, 2)
38 #define DPI_VID(x) UPDATE(x, 1, 0)
40 #define GEN_VID_RX(x) UPDATE(x, 6, 5)
57 #define VID_MODE_TYPE(x) UPDATE(x, 2, 1)
60 #define NULL_PKT_SIZE(x) UPDATE(x, 30, 21)
61 #define NUM_CHUNKS(x) UPDATE(x, 20, 11)
62 #define VID_PKT_SIZE(x) UPDATE(x, 10, 0)
80 #define HLINE_TIME(x) UPDATE(x, 31, 18)
[all …]
H A Dsamsung_mipi_dcphy.c31 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) macro
39 #define I_MUX_SEL(x) UPDATE(x, 6, 5)
44 #define S(x) UPDATE(x, 10, 8)
46 #define P(x) UPDATE(x, 5, 0)
50 #define M(x) UPDATE(x, 9, 0)
53 #define MRR(x) UPDATE(x, 13, 8)
55 #define MFR(x) UPDATE(x, 7, 0)
63 #define PLL_LOCK_CNT(x) UPDATE(x, 15, 0)
65 #define PLL_STB_CNT(x) UPDATE(x, 15, 0)
73 #define T_PHY_READY(x) UPDATE(x, 15, 0)
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/rk618/
H A Drk618_dsi.c37 #define TO_CLK_DIVIDSION(x) UPDATE(x, 15, 8)
38 #define TX_ESC_CLK_DIVIDSION(x) UPDATE(x, 7, 0)
46 #define DPI_COLOR_CODING(x) UPDATE(x, 4, 2)
47 #define DPI_VID(x) UPDATE(x, 1, 0)
49 #define GEN_VID_RX(x) UPDATE(x, 6, 5)
66 #define VID_MODE_TYPE(x) UPDATE(x, 2, 1)
69 #define NULL_PKT_SIZE(x) UPDATE(x, 30, 21)
70 #define NUM_CHUNKS(x) UPDATE(x, 20, 11)
71 #define VID_PKT_SIZE(x) UPDATE(x, 10, 0)
89 #define HLINE_TIME(x) UPDATE(x, 31, 18)
[all …]

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